參數(shù)資料
型號: DS1877T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 11/65頁
文件大?。?/td> 0K
描述: IC CTLR/MON SFP 1-2CH 28TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: SFP+ 控制器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 2.5mA
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
其它名稱: 90-1877T+TRL
19
Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
Digital I/O Pins
Four digital input pins and four digital output pins are
provided for monitoring and control.
LOS1, LOS2, and LOSOUT
When LOSC_ = 0 (Table 02h, Register 8Ah), the LOS_
pin is used to convert a standard comparator output for
LOS to an open-collector output. The output of the mux
can be read in the STATUS register (Lower Memory,
Register 6Eh) as the RXL bit. The RXL signal can be
inverted (INVLOS_ = 1) before driving the open-drain
output transistor using the XOR gate provided. Setting
LOSC_ = 1 configures the mux to be controlled by the
LOS LO QT alarm. The mux setting (stored in EEPROM)
does not take effect until VCC > POA, allowing the
EEPROM to recall.
INX, RSEL, OUTX, RSELOUT
Digital input pins INX and RSEL primarily serve to meet
the rate-select requirements of SFP and SFP+. They
can also serve as general-purpose inputs. OUTX and
RSELOUT are driven by a combination of the INX, RSEL,
and logic dictated by control registers in the EEPROM
(see Figure 11). The levels of INX and RSEL can be read
from the STATUS register (Lower Memory, Register 6Eh).
The open-drain output OUTX can be controlled and/or
inverted using the CNFGB register (Table 02h, Register
89h). The open-drain RSELOUT output is software con-
trolled and/or inverted through the STATUS register and
Figure 10. DAC Offset LUTs
Figure 11. Logic Diagram
DAC OFFSET LUTs (04h)[A2h/B2h]
EIGHT REGISTERS PER DAC
0
255
511
DELTA-SIGMA
DACs
767
1023
EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN
0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE
AND NEGATVE TEMPCO.
DAC
LUT
BITS
7:0
F8h
DAC
LUT
BITS
7:0
F9h
DAC
LUT
BITS
7:0
FAh
DAC
LUT
BITS
7:0
FBh
DAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
0
255
511
-40°C
-8°C
+8°C
+24°C +40°C +56°C +70°C +88°C +104°C
DELTA-SIGMA
DACs
767
1023
EACH OFFSET REGISTER CAN BE INDEPENDENTLY
SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS
EXAMPLE ILLUSTRATES POSITIVE TEMPCO.
DAC
LUT
BITS
7:0
F8h
DAC
LUT
BITS
7:0
F9h
DAC
LUT
BITS
7:0
FAh
DAC
LUT
BITS
7:0
FBh
DAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
DAC OFFSET LUTs (04h)[A2h/B2h]
EIGHT REGISTERS PER DAC
-40°C
-8°C
+8°C
+24°C +40°C +56°C +70°C +88°C +104°C
INVOUTX
INXC
INX
INXS
RXL
OUTX
INVRSOUT
INVLOSOUT
LOSC1
LOS1
LOS LO1
INVLOS1
MUX
RSELOUT
RSELC
RSEL
RSELS
= PINS
LOSOUT
LOS2
INVLOS2
LOSC2
LOS LO2
MUX
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