參數(shù)資料
型號: DS1877T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 40/65頁
文件大?。?/td> 0K
描述: IC CTLR/MON SFP 1-2CH 28TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: SFP+ 控制器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 2.5mA
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
其它名稱: 90-1877T+TRL
45
Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
Table 02h, Register 87h: DEVICE VER
Table 02h, Register 88h: CNFGA
FACTORY DEFAULT
DEVICE VERSION
READ ACCESS
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS
N/A
MEMORY TYPE
ROM
87h
DEVICE VERSION
BIT 7
BIT 0
Hardwired connections to show the device version.
FACTORY DEFAULT
C0h
READ ACCESS
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS
PW2 or (PW1 and RWTBL2)
A2h AND B2h MEMORY
Common A2h and B2h memory locations
MEMORY TYPE
Nonvolatile (SEE)
88h
RESERVED
ASEL
MASK
INVRSOUT
RESERVED
INVLOSOUT
BIT 7
BIT 0
BITS 7:5, 1
RESERVED
BIT 4
ASEL: Address select.
0 = (default) Device address is A2h for receiver 1 and B2h for receiver 2.
1 = DEVICE ADDRESS byte (Table 02h, Register 8Bh) is used as the device address for receiver
1. Receiver 2 remains at B2h.
BIT 3
MASK:
0 = (default) Alarm-enable row exists at Table 01h, Registers F8h–FFh. Table 05h, Registers F8h–
FFh are empty.
1 = Alarm-enable row exists at Table 05h, Registers F8h–FFh. Table 01h, Registers F8h–FFh are
empty.
BIT 2
INVRSOUT: Allow for inversion of the RSELOUT pin (see Figure 11).
0 = (default) RSELOUT is not inverted.
1 = RSELOUT is inverted.
BIT 0
INVLOSOUT: Allow for inversion of signal driven to the LOSOUT output pin.
0 = (default) LOSOUT is not inverted.
1 = LOSOUT signal is inverted.
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