參數(shù)資料
型號(hào)： DS1877T+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/65頁(yè)
文件大小： 0K
描述： IC CTLR/MON SFP 1-2CH 28TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： SFP+ 控制器
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： I²C
電流 - 電源： 2.5mA
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 28-TQFN-EP（5x5）
包裝： 帶卷 (TR)
其它名稱(chēng)： 90-1877T+TRL
20
Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
CNFGA register (Table 02h, Register 88h). External pul-
lup resistors must be provided on OUTX and RSELOUT
to realize high logic levels.
FAULT Output
FAULT can be triggered by all alarms, warnings, and
QTs. The six ADC alarms, warnings, and LOS QTs
require enabling (Table 01h/05h, Registers F8h and
FCh). Latching of the alarms is controlled by the CNFGB
and CNFGC registers (Table 02h, Registers 89h8Ah).
Die Identification
The device has an ID hardcoded in its die. Two registers
(Table 02h, Registers 86h87h) are assigned for this
feature. Register 86h reads 77h to identify the part as the
DS1877; Register 87h reads the present device version.
I2C Communication
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 12 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 12 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 12 for
applicable timing.
Bit Write: Transitions of SDA must occur during
the low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse
Figure 12. I2C Timing
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
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DS1878T TR 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:SFP+ Controller with Digital LDD Interface
DS1878T+ 功能描述:ADC / DAC多通道 SFP+ Controller w/ MAX3946&3945 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
DS1878T+T 功能描述:ADC / DAC多通道 SFP+ Controller w/ MAX3946&3945 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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