參數(shù)資料
型號(hào): DS2141AQN
廠商: Maxim Integrated Products
文件頁數(shù): 35/39頁
文件大?。?/td> 0K
描述: IC CONTROLLER T1 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 26
控制器類型: T1 控制器
接口: 并行/串行
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 10mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
DS2141A
5 of 39
PIN
SYMBOL
TYPE
DESCRIPTION
38
TLINK
I
Transmit Link Data. If enabled via TCR1.2, this pin will be
sampled during the F-bit time on the falling edge of TCLK for data
insertion into either the FDL stream (ESF) or the Fs-bit position
(D4) or the Z-bit position (ZBTSI). See Section 13 for timing
details.
39
TSYNC
I/O
Transmit Sync. A pulse at this pin will establish either frame or
multiframe boundaries for the DS2141A. Via TCR2.2, the DS2141A
can be programmed to output either a frame or multiframe pulse at
this pin. If this pin is set to output pulses at frame boundaries, it can
also be set via TCR2.4 to output double-wide pulses at signaling
frames. See Section 13 for timing details.
40
VDD
-
Positive Supply. 5.0 volts.
DS2141A REGISTER MAP
ADDRESS
R/W
REGISTER NAME
20
R/W
Status Register 1
21
R/W
Status Register 2
22
R/W
Receive Information
Register
23
R
Bipolar Violation/ESF
Error Event Count
Register 1
24
R
Bipolar Violation/ESF
Error Event Count
Register 2
25
R
CRC6 Count Register 1
26
R
CRC6 Count Register 2
27
R
Frame Error Count
Register
28
R
Receive FDL Register
29
R/W
Receive FDL Match
Register 1
2A
R/W
Receive FDL Match
Register 2
2B
R/W
Receive Control Register
1
2C
R/W
Receive Control Register
2
2D
R/W
Receive Mark Register 1
2E
R/W
Receive Mark Register 2
2F
R/W
Receive Mark Register 3
30
Not Assigned
31
Not Assigned
32
R/W
Transmit Channel
Blocking Register 1
33
R/W
Transmit Channel
Blocking Register 2
ADDRESS
R/W
REGISTER NAME
34
R/W
Transmit Channel
Blocking Register 3
35
R/W
Transmit Control
Register 1
36
R/W
Transmit Control
Register 2
37
R/W
Common Control
Register 1
38
R/W
Common Control
Register 2
39
R/W
Transmit Transparency
Register 1
3A
R/W
Transmit Transparency
Register 2
3B
R/W
Transmit Transparency
Register 3
3C
R/W
Transmit Idle Register 1
3D
R/W
Transmit Idle Register 2
3E
R/W
Transmit Idle Register 3
3F
R/W
Transmit Idle Definition
Register
60
R
Receive Signaling
Register 1
61
R
Receive Signaling
Register 2
62
R
Receive Signaling
Register 3
63
R
Receive Signaling
Register 4
64
R
Receive Signaling
Register 5
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