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參數(shù)資料
| 型號： | DS21448L |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU QUAD E1/T1/J1 128-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 管件 |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
12 of 60
PIN
I/O
FUNCTION
CES
I
Receive and Transmit Clock Select. Selects which RCLK edge to update RPOS and RNEG and
which TCLK edge to sample TPOS and TNEG. CES combines TCES and RCES.
0 = update RPOS/RNEG on rising edge of RCLK; sample TPOS/TNEG on falling edge of TCLK
1 = update RPOS/RNEG on falling edge of RCLK; sample TPOS/TNEG on rising edge of TCLK
TPD
I
Transmit Power-Down
0 = normal transmitter operation
1 = powers down the transmitter and tri-states TTIP and TRING pins
TX0/TX1
I
Transmit Data Source Select Bits 0 and 1. These inputs determine the source of the transmit
data (Table 4-B).
LOOP0/LOOP1
I
Loopback Select Bits 0 and 1. These inputs determine the active loopback mode (Table 4-A).
MM0/MM1
I
Monitor Mode Select Bits 0 and 1. These inputs determine if the receive equalizer is in a monitor
mode (Table 4-D).
RT1/RT0
I
Receive LIU Termination Select Bits 0 and 1. These inputs determine the receive termination
TEST
I
Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port).
Set low for normal operation. Useful in board-level testing.
HRST
I
Hardware Reset. Bringing
HRST low resets the DS21448, setting all control bits to the all-zero
default state.
MCLK
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and for jitter attenuation. A T1 1.544MHz
clock source is optional (Note 1). See Table 4-F for details.
BIS0/BIS1
I
Bus Interface Select Bit 0 and 1. Used to select bus interface option (Table 2-A).
EGL1–EGL4
I
Receive Equalizer Gain-Limit Select. These bits control the sensitivity of the receive equalizers
PBEO1–PBEO4
O
PRBS Bit-Error Output. The receiver constantly searches for a 2
15 - 1 PRBS (ETS = 0) or a
QRSS PRBS (ETS = 1). The pattern is chosen automatically by the value of the ETS pin. It
remains high if it is out of synchronization with the PRBS pattern. It goes low when synchronized
to the PRBS pattern. Any errors in the received pattern after synchronization cause a positive-
going pulse (with same period as E1 or T1 clock) synchronous with RCLK.
RCL1–RCL4
O
Receive Carrier Loss. An output that toggles high during a receive carrier loss.
RTIP1–RTIP4
I
RRING1–RRING4
I
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a
1:1 transformer to the line. See Section 7 for details.
BPCLK1–BPCLK4
O
Backplane Clock. A 16.384MHz clock output that is referenced to RCLK.
TTIP1–TTIP4
TRING1–TRING4
O
Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up
transformer to the line. See Section 7 for details.
RPOS1–RPOS4
O
Receive Positive Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
RNEG1–RNEG4
O
Receive Negative Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
RCLK1–RCLK4
O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of
signal at RTIP and RRING.
TPOS1–TPOS4
I
Transmit Positive Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
TNEG1–TNEG4
I
Transmit Negative Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
TCLK1–TCLK4
I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit
side formatter. It can be sourced internally by MCLK or RCLK. See Common Control Register 1
and Figure 1-3.
JTRST
I
JTAG Reset
JTMS
I
JTAG Mode Select
JTCLK
I
JTAG Clock
JTDI
I
JTAG Data In
JTDO
O
JTAG Data Out
VSM
I
Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.
TVDD1–TVDD4
–
3.3V, ±5% Transmitter Positive Supply
VDD1–VDD4
—
3.3V, ±5% Positive Supply
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21448L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448LDK | 功能描述:KIT DESIGN LIU DS21448L T1/J1/E1 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS21448LN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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