參數(shù)資料
型號(hào): DS21448L
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 43/60頁(yè)
文件大?。?/td> 0K
描述: IC LIU QUAD E1/T1/J1 128-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: T1/E1/J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21448 3.3V T1/E1/J1 Quad Line Interface
48 of 60
PIN
BIT
BGA
LQFP
NAME
I/O
M6
45
JTDI
I
M7
46
JTDO
O
55
M8
68
BIS1
I
M9
104
TVDD4
PIN
BIT
BGA
LQFP
NAME
I/O
10
M10
25
RNEG4
O
61
ADRScntl
66
M11
55
TPOS4
I
34
M12
108
PBTS
I
Note 1: 0 = Dn/ADn are inputs; 1 = Dn/ADn are outputs.
Note 2: 0 =
INT is an input; 1 = INT is an output.
9. OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
-1.0V to +6.0V
Operating Temperature Range for DS21448TN
-40°C to +85°C
Storage Temperature Range
-55°C to +125°C
Soldering Temperature
See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic 1
VIH
2.2
5.5
V
Logic 0
VIL
-0.3
+0.8
V
Supply for 3.3V Operation
VDD
(Note 1)
3.135
3.3
3.465
V
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
CIN
5
pF
Output Capacitance
COUT
7
pF
DC CHARACTERISTICS
(VDD = 3.3V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Leakage
IIL
(Note 2)
-1.0
+1.0
A
Output Leakage
ILO
(Note 3)
+1.0
A
Output Current (2.4V)
IOH
-1.0
mA
Output Current (0.4V)
IOL
+4.0
mA
Supply Current at 3.3V
IDD
(Notes 4, 5)
320
400
mA
Power Dissipation at 3.3V
PDD
(Notes 4, 5)
1.06
1.32
W
Note 1: Applies to VDD.
Note 2: 0.0V < VIN < VDD.
Note 3: Applied to
INT when tri-stated.
Note 4: TCLK = MCLK = 2.048MHz.
Note 5: Power dissipation with all ports active, TTIP and TRING driving a 30
load, for an all-ones data density.
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