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參數(shù)資料
| 型號： | DS21448L |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU QUAD E1/T1/J1 128-LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 管件 |
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DS21448 3.3V T1/E1/J1 Quad Line Interface
14 of 60
4. PORT OPERATION
4.1 Hardware Mode
The DS21448 supports a hardware configuration mode that allows the user to configure the device by setting levels
on the device’s pins. This mode allows the DS21448 configuration without the use of a microprocessor, simplifying
designs. Not all of the device features are supported in the hardware mode.
In hardware mode (BIS0 = 1, BIS1 = 1) several pins have been redefined so they can be used for initializing the
DS21448. Refer to Table 2-B and Table 2-E for pin assignment and definition. Because of limited pin count, several
functions have been combined and affect all four channels in the device and/or treat the receive and transmit paths
as one block. Restrictions when using the hardware mode include the following:
BPCLK pins only output a 16.384MHz signal.
The RCL/LOTC pins are designated to RCL.
The RHBE and THBE control bits are combined and controlled by HBE.
RSCLKE and TSCLKE bits are combined and controlled by SCLKE.
TCES and RCES are combined and controlled by CES.
The transmitter functions are combined and controlled by TX1 and TX0.
Loopback functions are controlled by LOOP1 and LOOP0.
JABDS defaults to 128-bit buffer depth.
All other control bits default to logic 0.
Table 4-A. Loopback Control in Hardware Mode
LOOPBACK
SYMBOL
LOOP1
LOOP0
Remote Loopback
RLB
1
Local Loopback
LLB
1
0
Analog Loopback
ALB
0
1
No Loopback
—
0
Table 4-B. Transmit Data Control in Hardware Mode
TRANSMIT DATA
SYMBOL
TX1
TX0
Unframed All Ones
TUA1
1
Alternating Ones and Zeros
TAOZ
1
0
PRBS
TPRBSE
0
1
TPOS and TNEG
—
0
Table 4-C. Receive Sensitivity Settings in Hardware Mode
EGL
ETS
RECEIVE SENSITIVITY (dB)
0
0 (E1)
-12 (short haul)
1
0 (E1)
-43 (long haul)
1
1 (T1)
-30 (limited long haul)
0
1 (T1)
-36 (long haul)
Table 4-D. Monitor Gain Settings in Hardware Mode
MM1
MM0
INTERNAL LINEAR GAIN BOOST (dB)
0
Normal operation (no boost)
0
1
20
1
0
26
1
32
Table 4-E. Internal Rx Termination Select in Hardware Mode
RT1
RT0
INTERNAL RECEIVE
TERMINATION CONFIGURATION
0
Internal receive-side termination disabled
0
1
Internal receive-side 120 enabled
1
0
Internal receive-side 100 enabled
1
Internal receive-side 75 enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21448L+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448L+W | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448LDK | 功能描述:KIT DESIGN LIU DS21448L T1/J1/E1 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標準包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS21448LN | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21448LN+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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