參數(shù)資料
型號: DS2181AQN+
廠商: Maxim Integrated Products
文件頁數(shù): 31/32頁
文件大小: 0K
描述: IC TXRX CEPT PRIMARY RATE 44PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 26
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: CEPT
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
DS2181A
8 of 32
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
TCR: TRANSMIT CONTROL REGISTER Figure 4
(MSB)
(LSB)
TUA1
TSS
TSM
INBS
NBS
XBS
TSA1
ODM
SYMBOL
POSITION
NAME AND DESCRIPTION
TUA1
TCR.7
Transmit Unframed All 1’s.
0 = Normal operation.
1 = Replace outgoing data at TPOS and TNEG with unframed all
1’s code.
TSS
TCR.6
Transmit Signaling Select
1
0 = Signaling data embedded in the serial bit stream is sampled at
TSER during timeslot 16.
1 = Signaling data is channel associated and sampled at TSD as
shown in Table 6.
TSM
TCR.5
Transmit Signaling Mode
1
0 = Channel Associated Signaling (CAS).
1 = Common Channel Signaling (CCS).
INBS
TCR.4
International Bit Select
0 = Sample international bit at TIND.
1 = Outgoing international bit = TINR.7.
NBS
TCR.3
National Bit Select
0 = Sample national bits at TIND.
1 = Source outgoing national bits from TINR.4 through TINR.0.
XBS
TCR.2
Extra Bit Select
0 = Sample extra bits at TXD.
1 = Source extra bits from TXR.0 through TXR.1 and TXR.3.
TSA1
TCR.1
Transmit Signaling All 1’s
0 = Normal operation.
1 = Force contents of timeslot 16 in all frames to all 1’s.
ODM
TCR.0
Output Data Mode
0 = TPOS and TNEG outputs are 100% duty cycle.
1 = TPOS and TNEG outputs are 50% duty cycle.
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