參數(shù)資料
型號: DS2181AQN+
廠商: Maxim Integrated Products
文件頁數(shù): 32/32頁
文件大?。?/td> 0K
描述: IC TXRX CEPT PRIMARY RATE 44PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 26
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: CEPT
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
DS2181A
9 of 32
NOTE:
1. When the common channel signaling mode is enabled (TCR.5 = 1), the TSD input is disabled
internally; all timeslot 16 data is sampled at TSER.
CCR: COMMON CONTROL REGISTER Figure 5
(MSB)
(LSB)
-
TAFP
THDE
RHDE
TCE
RCE
SAS
LLB
SYMBOL
POSITION
NAME AND DESCRIPTION
-
CCR.7
Reserved; must be 0 for proper operation.
TAFP
CCR.6
Transmit Align Frame Position
1
When clear, the CAS multiframe begins with a frame containing
the frame alignment signal. When set, the CAS multiframe begins
with a frame not containing the frame alignment signal.
THDE
CCR.5
Transmit HDB3 Enable
0 = Outgoing data at TPOS and TNEG is AMI coded.
1 = Outgoing data at TPOS and TNEG is HDB3 coded.
RHDE
CCR.4
Receive HDB3 Enable
0 = Incoming data at RPOS and RNEG is AMI coded.
1 = Incoming data is RPOS and RNEG is HDB3 coded.
TCE
CCR.3
Transmit CRC4 Enable
When set, outgoing international bit positions in frames 0 through
12 and 14 are replaced by CRC4 multiframe alignment and
checksum words.
RCE
CCR.2
Receive CRC4 Enable
0 = Disable CRC4 multiframe synchronizer.
1 = Enable CRC4 synchronizer; search for CRC4 multiframe
alignment once frame alignment complete.
SAS
CCR.1
Sync Algorithm Select
0 = Use old DS2181 sync algorithm
1 = Use new DS2181A sync algorithm
LLB
CCR.0
Local Loopback
0 = Normal operation.
1 = Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG,
and RCLK.
NOTES:
1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3 = 1); its state does not
affect CCS framing (RCR.5 = 1).
2. CCR is considered a receive register and operates from RCLK and SCLK.
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