- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97867 > DS21FT44 (MAXIM INTEGRATED PRODUCTS INC) DATACOM, FRAMER, PBGA300 PDF資料下載
參數(shù)資料
| 型號(hào)： | DS21FT44 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300 |
| 文件頁(yè)數(shù)： | 55/117頁(yè) |
| 文件大?。?/td> | 691K |
| 代理商： | DS21FT44 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
DS21FT44/DS21FF44
42 of 117
CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex)
(MSB)
(LSB)
—
TCLKSRC
RESR
TESR
SYMBOL
POSITION
NAME AND DESCRIPTION
—
CCR6.7
Not Assigned. Should be set to zero when written
—
CCR6.6
Not Assigned. Should be set to zero when written
—
CCR6.5
Not Assigned. Should be set to zero when written
—
CCR6.4
Not Assigned. Should be set to zero when written
—
CCR6.3
Not Assigned. Should be set to zero when written
TCLKSRC
CCR6.2
Transmit Clock Source Select. This function allows the user
to internally select RCLK as the clock source for the transmit
side formatter.
0 = transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = transmit side formatter clocked with RCLK.
RESR
CCR6.1
Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this bit
set high.
TESR
CCR6.0
Transmit Elastic Store Reset. Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this bit
set high.
11.
STATUS AND INFORMATION REGISTERS
There is a set of seven registers per framer that contain information on the current real time status of a
framer in the DS21Q44, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register
(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.
The specific details on the four registers pertaining to the HDLC controller are covered in Section 19 but
they operate the same as the other status registers in the DS21Q44 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The
Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and
a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again (or in the case of the
RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still
present).
The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The byte
written to the register will inform the framer which bits the user wishes to read and have cleared. The
user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and
a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with the latest information. When a zero is
written to a bit position, the read register will not be updated and the previous value will be held. A write
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q352 | DATACOM, PCM TRANSCEIVER, PBGA256 |
| DS21Q354 | DATACOM, PCM TRANSCEIVER, PBGA256 |
| DS21Q41BT | DATACOM, FRAMER, PQFP128 |
| DS21Q42TN | DATACOM, FRAMER, PQFP128 |
| DS21Q42T | DATACOM, FRAMER, PQFP128 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FT44+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT44N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q348 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q348B | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。