參數(shù)資料
型號(hào): DS21FT44
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù): 78/117頁
文件大?。?/td> 691K
代理商: DS21FT44
DS21FT44/DS21FF44
63 of 117
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCC1 (A4)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCC2 (A5)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCC3 (A6)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
RCC4 (A7)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1–32
RCC1.0–4.7
Receive Code Insertion Control Bits
0 = do not insert data from the RC register into the receive data
stream
1 = insert data from the RC register into the receive data
stream
16.
CLOCK BLOCKING REGISTERS
The Receive Channel blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins respectively.
(The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low
during individual channels). These outputs can be used to block clocks to a USART or LAPD controller
in ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin
will be held high during the entire corresponding channel time. See the timing in Section 22 for an
example. The TCBRs have alternate mode of use. By the CCR3.6 bit, the user has the option to use the
TCBRs to determine on a channel by channel basis, which signaling bits are to be inserted by the TSRs
(the corresponding bit in the TCBRs = 1) and which are to be sourced from the TSER or TSIG pins (the
corresponding bit in the TCBR = 0). See the timing in Section 22 for an example.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS
(Address = 2B to 2E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCBR1 (2B)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCBR2 (2C)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCBR3 (2D)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
RCBR4 (2E)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1–32
RCBR1.0–4.7
Receive Channel Blocking Control Bits
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
相關(guān)PDF資料
PDF描述
DS21Q352 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q41BT DATACOM, FRAMER, PQFP128
DS21Q42TN DATACOM, FRAMER, PQFP128
DS21Q42T DATACOM, FRAMER, PQFP128
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