參數(shù)資料
型號(hào): DS21FT44N+
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 46/117頁(yè)
文件大小: 0K
描述: IC FRAMER 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類(lèi)型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 225mA
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
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DS21FT44/DS21FF44
34 of 117
Table 10–1. SYNC/RESYNC CRITERIA
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N
and N + 2, and FAS not
present in frame N + 1
Three consecutive incorrect FAS
received
Alternate (RCR1.2 = 1) the above
criteria is met or three
consecutive incorrect bit 2 of
non-FAS received
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment
words found within 8 ms
915 or more CRC4 code words
out of 1000 received in error
G.706
4.2 and 4.3.2
CAS
Valid MF alignment word
found and previous
timeslot 16 contains code
other than all zeros
Two consecutive MF alignment
words received in error
G.732 5.2
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa8S
RCR2.7
Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit
position; set to zero to force RLCLK low during Sa8 bit
position. See Section 22 for timing details.
Sa7S
RCR2.6
Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit
position; set to zero to force RLCLK low during Sa7 bit
position. See Section 22 for timing details.
Sa6S
RCR2.5
Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit
position; set to zero to force RLCLK low during Sa6 bit
position. See Section 22 for timing details.
Sa5S
RCR2.4
Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit
position; set to zero to force RLCLK low during Sa5 bit
position. See Section 22 for timing details.
Sa4S
RCR2.3
Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit
position; set to zero to force RLCLK low during Sa4 bit
position. See Section 22 for timing details.
RBCS
RCR2.2
Receive Side Backplane Clock Select
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz
RESE
RCR2.1
Receive Side Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
RCR2.0
Not Assigned. Should be set to zero when written.
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DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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