參數(shù)資料
型號: DS21FT44N+
廠商: Maxim Integrated Products
文件頁數(shù): 89/117頁
文件大?。?/td> 0K
描述: IC FRAMER 4X4 16CH 300-BGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 225mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT44/DS21FF44
73 of 117
19.4. HDLC REGISTER DESCRIPTION
HCR: HDLC CONTROL REGISTER (Address=B0 Hex)
(MSB)
(LSB)
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOL
POSITION
NAME AND DESCRIPTION
HCR.7
Not Assigned. Should be set to zero.
RHR
HCR.6
Receive HDLC Reset. A 0-to-1 transition resets the receive
HDLC controller. Must be cleared and set again for a
subsequent reset.
TFS
HCR.5
Transmit Flag/Idle Select
0 = 7Eh.
1 = FFh.
THR
HCR.4
Transmit HDLC Reset. A 0-to-1 transition resets the
transmit HDLC controller. Must be cleared and set again for a
subsequent reset.
TABT
HCR.3
Transmit Abort. A 0-to-1 transition causes the FIFO contents
to be dumped and one FEh abort to be sent followed by 7Eh or
FFh flags/idle until a new packet is initiated by writing new
data into the FIFO. Must be cleared and set again for a
subsequent abort to be sent.
TEOM
HCR.2
Transmit End of Message. Should be set to a one just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD
HCR.0
Transmit CRC Defeat
0 = enable CRC generation (normal operation)
1 = disable CRC generation
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