參數(shù)資料
型號: DS21FT44N+
廠商: Maxim Integrated Products
文件頁數(shù): 79/117頁
文件大?。?/td> 0K
描述: IC FRAMER 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 225mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT44/DS21FF44
64 of 117
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address = 22 to 25 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCBR1 (22)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCBR2 (23)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCBR3 (24)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TCBR4 (25)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1–32
TCBR1.0–4.7
Transmit Channel Blocking Control Bits
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
Note: If CCR3.6 = 1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER
(or TSIG if CCR3.2 = 1) and a one implies that signaling data for that channel is to be sourced from the
Transmit Signaling (TS) registers. See definition below.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1
(MSB)
(LSB)
CH20
CH4
CH19
CH3
CH18
CH2
CH17*
CH1*
TCBR1 (22)
CH24
CH8
CH23
CH7
CH22
CH6
CH21
CH5
TCBR2 (23)
CH28
CH12
CH27
CH11
CH26
CH10
CH25
CH9
TCBR3 (24)
CH32
CH16
CH31
CH15
CH30
CH14
CH29
CH13
TCBR4 (25)
*CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm
bits.
17.
ELASTIC STORES OPERATION
Each framer in the DS21Q44 contains dual two-frame (512 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the E1 data stream to 1.544Mbps (or a multiple of 1.544Mbps), which is the T1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock, which can be 1.544MHz or
2.048MHz. The backplane clock can burst at rates up to 8.192MHz. Both elastic stores contain full
controlled slip capability, which is necessary for this second purpose. Both elastic stores within a framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to
them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or
disabled and vice versa. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz
backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset (CCR6.0
and CCR6.1) function forces the elastic stores to a depth of one frame unconditionally. Data is lost during
the reset. The second method, the Elastic Store Align (CCR5.5 and CCR5.6) forces the elastic store depth
to a minimum depth of half a frame only if the current pointer separation is already less then half a frame.
If a realignment occurs data is lost. In both mechanisms, independent resets are provided for both the
receive and transmit elastic stores.
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