參數(shù)資料
型號： DS21Q48A3N
廠商： Maxim Integrated Products
文件頁數(shù)： 16/73頁
文件大小： 0K
描述： IC LIU 5V E1/T1/J1 144-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 144-BBGA
供應(yīng)商設(shè)備封裝： 144-PBGA（17x17）
包裝： 管件
DS2148/DS21Q48
23 of 73
3 HARDWARE MODE
In hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for
initializing the DS2148. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The
RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0.
The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11
while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE at
pin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The
transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). LOOP1 (pin 17)
and LOOP0 (pin 16) control the loopback functions. All other control bits default to the logic 0 setting.
3.1 Register Map
Table 3-1. Register Map
NAME
REGISTER NAME
R/W
PARALLEL
PORT MODE
SERIAL PORT
MODE
(Notes 2–5)
(msb)
(lsb)
CCR1
Common Control Register 1
R/W
00h
B000 000A
CCR2
Common Control Register 2
R/W
01h
B000 001A
CCR3
Common Control Register 3
R/W
02h
B000 010A
CCR4
Common Control Register 4
R/W
03h
B000 011A
CCR5
Common Control Register 5
R/W
04h
B000 100A
CCR6
Common Control Register 6
R/W
05h
B000 101A
SR
Status Register
R
06h
B000 110A
IMR
Interrupt Mask Register
R/W
07h
B000 111A
RIR1
Receive Information Register 1
R
08h
B001 000A
RIR2
Receive Information Register 2
R
09h
B001 001A
IBCC
In-Band Code Control Register
R/W
0Ah
B001 010A
TCD1
Transmit Code Definition Register 1
R/W
0Bh
B001 011A
TCD2
Transmit Code Definition Register 2
R/W
0Ch
B001 100A
RUPCD1
Receive Up Code Definition Register 1
R/W
0Dh
B001 101A
RUPCD2
Receive Up Code Definition Register 2
R/W
0Eh
B001 110A
RDNCD1
Receive Down Code Definition Register 1
R/W
0Fh
B001 111A
RDNCD2
Receive Down Code Definition Register 2
R/W
10h
B010 000A
ECR1
Error Count Register 1
R
11h
B010 001A
ECR2
Error Count Register 2
R
12h
B010 010A
TEST1
Test 1
R/W
13h
B010 011A
TEST2
Test 2
R/W
14h
B010 100A
TEST3
Test 3
R/W
15h
B010 101A
–
Note 1
–
NOTES:
1) Register addresses 16h to 1Fh do not exist.
2) In the Serial Port Mode, the LSB is on the right hand side.
3) In the Serial Port Mode, data is read and written LSB first.
4) In the Serial Port Mode, the A bit (the LSB) determines whether the access is a read (A = 1) or a write
(A = 0).
5) In the Serial Port Mode, the B bit (the MSB) determines whether the access is a burst access (B = 1) or a single
register access (B = 0).
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