參數(shù)資料
型號(hào)： DS21Q48A3N
廠商： Maxim Integrated Products
文件頁數(shù)： 38/73頁
文件大小： 0K
描述： IC LIU 5V E1/T1/J1 144-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 144-BBGA
供應(yīng)商設(shè)備封裝： 144-PBGA（17x17）
包裝： 管件
DS2148/DS21Q48
43 of 73
RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2
(MSB)
(LSB)
C15
C14
C13
C12
C11
C10
C9
C8
SYMBOL
POSITION
DESCRIPTION
C15
RDNCD2.7
Receive Down Code Definition Bit 15
C14
RDNCD2.6
Receive Down Code Definition Bit 14
C13
RDNCD2.5
Receive Down Code Definition Bit 13
C12
RDNCD2.4
Receive Down Code Definition Bit 12
C11
RDNCD2.3
Receive Down Code Definition Bit 11
C10
RDNCD2.2
Receive Down Code Definition Bit 10
C9
RDNCD2.1
Receive Down Code Definition Bit 9
C8
RDNCD2.0
Receive Down Code Definition Bit 8
6.2 Loopbacks
6.2.1 Remote Loopback (RLB)
When RLB (CCR6.6) is enabled, the DS2148 is placed into remote loopback. In this loopback, data from
the clock/data recovery state machine will be looped back to the transmit path passing through the jitter
attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented at
TPOS and TNEG will be ignored (Figure 1-1).
If the Automatic Remote Loopback Enable (CCR6.5) is set to a one, the DS2148 will automatically go
into remote loopback when it detects the loop up code programmed in the Receive Up Code Definition
Registers (RUPCD1 and RUPCD2) for a minimum of 5 seconds. When the DS2148 detects the loop
down code programmed in the Receive Loop Down Code Definition registers (RDNCD1 and RDNCD2)
for a minimum of 5 seconds, the DS2148 will come out of remote loopback. Setting ARLBE to a zero
also can disable the ARLB.
6.2.2 Local Loopback (LLB)
When LLB (CCR6.7) is set to a one, the DS2148 is placed into local loopback. In this loopback, data on
the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through the
jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at
RTIP and RRING will be ignored. If Transmit Unframed All Ones (CCR3.7) is set to a one while in LLB,
TTIP and TRING will transmit all ones while TCLK and TPOS/TNEG will be looped back to RCLK and
RPOS/RNEG (Figure 1-1).
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