參數(shù)資料
型號: DS21Q48A3N
廠商: Maxim Integrated Products
文件頁數(shù): 25/73頁
文件大?。?/td> 0K
描述: IC LIU 5V E1/T1/J1 144-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 144-BBGA
供應(yīng)商設(shè)備封裝: 144-PBGA(17x17)
包裝: 管件
DS2148/DS21Q48
31 of 73
4.1 Device Power-Up and Reset
The DS2148 will reset itself upon power-up, setting all writeable registers to 00h and clearing the status
and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After
the power supplies have settled following power-up, initialize all control registers to the desired settings,
then toggle the LIRST bit (CCR3.2). The DS2148 can be reset at anytime to the default settings by
bringing
HRST (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB)
(LSB)
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
SYMBOL
POSITION
DESCRIPTION
L2
CCR4.7
Line Build-Out Select Bit 2. Sets the transmitter build out
L1
CCR4.6
Line Build-Out Select Bit 1. Sets the transmitter build out
L0
CCR4.5
Line Build-Out Select Bit 0. Sets the transmitter build out
EGL
CCR4.4
Receive Equalizer Gain Limit. This bit controls the sensitivity
of the receive equalizer (Table 4-2).
JAS
CCR4.3
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS
CCR4.2
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA
CCR4.1
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD
CCR4.0
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and
TRING pins
Table 4-2. Receive Sensitivity Settings
EGL
(CCR4.4)
ETS
(CCR1.7)
RECEIVE SENSITIVITY
0
0 (E1)
-12dB (short haul)
1
0 (E1)
-43dB (long haul)
1
1 (T1)
-30dB (limited long haul)
0
1 (T1)
-36dB (long haul)
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