參數(shù)資料
型號(hào): DS21Q48N
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 13/73頁(yè)
文件大小: 0K
描述: IC LIU E1/T1/J1 4X 5V LONG144BGA
標(biāo)準(zhǔn)包裝: 90
類(lèi)型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 144-BBGA
供應(yīng)商設(shè)備封裝: 144-PBGA(17x17)
包裝: 管件
DS2148/DS21Q48
20 of 73
Table 2-8. Loopback Control in Hardware Mode
LOOPBACK
SYMBOL
CONTROL BIT
LOOP1
LOOP0
Remote Loopback
RLB
CCR6.6
1
Local Loopback
LLB
CCR6.7
1
0
Analog Loopback
ALB
CCR6.4
0
1
No Loopback
0
Table 2-9. Transmit Data Control in Hardware Mode
TRANSMIT DATA
SYMBOL
CONTROL
BIT
TX1
TX0
Transmit Unframed All Ones
TUA1
CCR3.7
1
Transmit Alternating Ones and Zeros
TAOZ
CCR3.5
1
0
Transmit PRBS
TPRBSE
CCR3.4
0
1
TPOS and TNEG
0
Table 2-10. Receive Sensitivity Settings
EGL
(CCR4.4)
ETS
(CCR1.7)
RECEIVE SENSITIVITY
0
0 (E1)
-12dB (short haul)
1
0 (E1)
-43dB (long haul)
1
1 (T1)
-30dB (limited long haul)
0
1 (T1)
-36dB (long haul)
Table 2-11. Monitor Gain Settings
MM1
(CCR5.5)
MM0
(CCR5.4)
INTERNAL LINEAR
GAIN BOOST (dB)
0
Normal operation (no boost)
0
1
20
1
0
26
1
32
Table 2-12. Internal Rx Termination Select
RT1
(CCR5.1)
RT0
(CCR5.0)
INTERNAL RECEIVE
TERMINATION CONFIGURATION
0
Internal receive-side termination disabled
0
1
Internal receive-side 120
enabled
1
0
Internal receive-side 100
enabled
1
Internal receive-side 75
enabled
Table 2-13. MCLK Selection
MCLK
JAMUX
(CCR1.3)
ETS
(CCR1.7)
2.048MHz
0
2.048MHz
1
1.544MHz
0
1
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