參數(shù)資料
型號(hào)： DS21Q48N
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 7/73頁(yè)
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 4X 5V LONG144BGA
標(biāo)準(zhǔn)包裝： 90
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 144-BBGA
供應(yīng)商設(shè)備封裝： 144-PBGA（17x17）
包裝： 管件
DS2148/DS21Q48
15 of 73
Table 2-5. Pin Descriptions in Serial Port Mode (Sorted by Pin Name,
DS2148T)
NAME
PIN
I/O
FUNCTION
BIS0/BIS1
32/33
I
Bus Interface Select Bits 0 & 1. Used to select bus interface option. See
Table 2-1 for details.
BPCLK
31
O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
clock output that is referenced to RCLK selectable via CCR5.7 and
CCR5.6. In hardware mode, defaults to 16.384MHz output.
CS
1
I
Active-Low Chip Select. Must be low to read or write to the device.
HRST
29
I
Hardware Reset. Bringing
HRST low will reset the DS2148 setting all
control bits to their default state of all zeros.
ICES
8
I
Input Clock Edge Select. Selects whether the serial port data input (SDI)
is sampled on rising (ICES =0) or falling edge (ICES = 1) of SCLK.
INT
23
O
Active-Low Interrupt. Flags host controller during conditions and change
of conditions defined in the Status Register. Active low, open drain output.
MCLK
30
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is
applied at this pin. This clock is used internally for both clock/data
recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is
optional. See Note 1 on clock accuracy at the end of this table.
NA
-
I
Not Assigned. Should be tied low.
OCES
9
I
Output Clock Edge Select. Selects whether the serial port data output
(SDO) is valid on the rising (OCES = 1) or falling edge (OCES = 0) of
SCLK.
PBEO
24
O
PRBS Bit Error Output. The receiver will constantly search for a 215-1
or a 220-1 PRBS depending on the ETS bit setting (CCR1.7). Remains
high if out of synchronization with the PRBS pattern. Goes low when
synchronized to the PRBS pattern. Any errors in the received pattern after
synchronization will cause a positive going pulse (with same period as E1
or T1 clock) synchronous with RCLK. PRBS bit errors can also be
reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.
RCLK
40
O
Receive Clock. Buffered recovered clock from the line. Synchronous to
MCLK in absence of signal at RTIP and RRING.
RCL/LOTC
25
O
Receive Carrier Loss/Loss of Transmit Clock. An output which will
toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high
if the TCLK pin has not been toggled for 5
s ± 2 s (CCR2.7 = 1).
CCR2.7 defaults to logic 0 when in hardware mode.
RNEG
39
O
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the
falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line
interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause a
positive-going pulse synchronous with RCLK at RNEG. See Section 6.4
for details.
RPOS
38
O
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the
falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the line
interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause a
positive-going pulse synchronous with RCLK at RNEG. See Section 6.4
for details.
RTIP/RRING
27/28
I
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These
pins connect via a 1:1 transformer to the line. See Section 5 for details.
SCLK
5
I
Serial Clock. Serial bus clock input.
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