參數(shù)資料
型號(hào): DS21Q48N
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/73頁(yè)
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 4X 5V LONG144BGA
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 144-BBGA
供應(yīng)商設(shè)備封裝: 144-PBGA(17x17)
包裝: 管件
DS2148/DS21Q48
16 of 73
NAME
PIN
I/O
FUNCTION
SDI
6
I
Serial Data Input. Sampled on rising edge (ICES = 0) or the falling edge
(ICES = 1) of SCLK.
SDO
7
O
Serial Data Output. Valid on the falling edge (OCES = 0) or the rising
edge (OCES = 1) of SCLK.
TCLK
43
I
Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced internally
by MCLK or RCLK. See Common Control Register 1 and Figure 1-3.
TEST
26
I
Tri-State Control. Set high to tri-state all outputs and I/O pins (including
the parallel control port). Set low for normal operation. Useful in board
level testing.
TNEG
42
I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or
the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto
the line.
TPOS
41
I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the
rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the
line.
TTIP/TRING
34/37
O
Transmit Tip and Ring . Analog line driver outputs. These pins connect
via a step-up transformer to the line. See Section 5 for details.
VDD
21/36
-
5.0V ±5% Positive Supply
VSM
20
I
Voltage Supply Mode. Should be tied high for 5V operation.
VSS
22/35
-
Signal Ground
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