參數(shù)資料
型號: DS21Q50L
廠商: Maxim Integrated Products
文件頁數(shù): 25/87頁
文件大小: 0K
描述: IC TRANSCEIVER E1 QUAD 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: AIS 警報檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠(yuǎn)程檢測器和發(fā)生器
DS21Q50
31 of 87
Register Name:
CCR5
Register Description:
Common Control Register 5
Register Address:
16 Hex
Bit
7
6
5
4
3
2
1
0
Name
LIUODO
CDIG
LIUSI
IRTSEL
TPRBS1
TPRBS0
RPRBS1
RPRBS0
NAME
BIT
FUNCTION
LIUODO
7
Line Interface Open-Drain Option. This control bit determines whether the TTIP and
TRING outputs are open drain or not. The line driver outputs can be forced open drain to
allow 6V peak pulses to be generated or to allow the creation of a very low-power
interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
CDIG
6
Customer Disconnect Indication Generator. This control bit determines whether the line
interface generates an unframed ...1010... pattern at TTIP and TRING instead of the
normal data pattern.
0 = generate normal data at TTIP and TRING
1 = generate a ...1010... pattern at TTIP and TRING
LIUSI
5
Line Interface G.703 Synchronization Interface Enable. This control bit determines
whether the line receiver should handle a normal E1 signal (Section 6 of G.703) or a
2.048MHz synchronization signal (Section 10 of G.703). This control has no affect on
the line interface transmitter.
0 = line receiver configured to support a normal E1 signal
1 = line receiver configured to support a synchronization signal
IRTSEL
4
Receive Termination Select. This function applies internal parallel resistance to the
normal 120
W external termination to create a 75W termination.
0 = normal 120
W external termination
1 = internally adjust receive termination to 75
W
TPRBS1
3
Transmit PRBS Mode Bit 1 (Table 8-1)
TPRBS0
2
Transmit PRBS Mode Bit 0 (Table 8-1)
RPRBS1
1
Receive PRBS Mode Bit 1 (Table 8-2)
RPRBS0
0
Receive PRBS Mode Bit 0 (Table 8-2)
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