參數(shù)資料
型號(hào): DS21Q50L
廠商: Maxim Integrated Products
文件頁數(shù): 46/87頁
文件大?。?/td> 0K
描述: IC TRANSCEIVER E1 QUAD 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: AIS 警報(bào)檢測(cè)器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測(cè)器,遠(yuǎn)程檢測(cè)器和發(fā)生器
DS21Q50
50 of 87
14.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
On the receiver, the RAF and RNAF registers always report the data as it is received in the additional (Sa)
and international (Si) bit locations. The RAF and RNAF registers are updated with the setting of the
receive align frame bit in status register 2 (SR2.6). The host can use the SR2.6 bit to know when to read
the RAF and RNAF registers. It has 250
ms to retrieve the data before it is lost.
On the transmitter, data is sampled from the TAF and TNAF registers with the setting of the transmit
align frame bit in status register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250s to update the data or else the old data is retransmitted. Data in the
Si bit position is overwritten if either the framer is programmed (1) to source the Si bits from the TSER
pin, (2) in the CRC4 mode, or (3) to have automatic E-bit insertion enabled. Data in the Sa-bit position is
overwritten if any of the TCR.3 to TCR.7 bits is set to 1. Please see the register descriptions for TCR for
more details.
Register Name:
RAF
Register Description:
Receive Align Frame Register
Register Address:
28 Hex
Bit
7
6
5
4
3
2
1
0
Name
Si
0
1
0
1
NAME
BIT
FUNCTION
Si
7
International Bit
0
6
Frame Alignment Signal Bit
0
5
Frame Alignment Signal Bit
1
4
Frame Alignment Signal Bit
1
3
Frame Alignment Signal Bit
0
2
Frame Alignment Signal Bit
1
Frame Alignment Signal Bit
1
0
Frame Alignment Signal Bit
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