參數(shù)資料
型號: DS21Q59L
廠商: Maxim Integrated Products
文件頁數(shù): 26/76頁
文件大?。?/td> 0K
描述: IC TXRX E1 QUAD 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: AIS 警報(bào)檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠(yuǎn)程檢測器和發(fā)生器
DS21Q59 Quad E1 Transceiver
32 of 76
Register Name:
SR2
Register Description:
Status Register 2
Register Address:
0B Hex
Bit #
7
6
5
4
3
2
1
0
Name
RMF
RAF
TMF
SEC
TAF
LOTC
RCMF
PRBSD
NAME
BIT
FUNCTION
RMF
7
Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is
enabled or not) on receive multiframe boundaries.
RAF
6
Receive Align Frame. Set every 250s at the beginning of align frames.
Used to alert the host that Si and Sa bits are available in the RAF and
RNAF registers.
TMF
5
Transmit Multiframe. Set every 2ms (regardless if CRC4 is enabled) on
transmit multiframe boundaries.
SEC
4
One-Second Timer. Set on increments of one second based on RCLK. If
CCR2.7 = 1, this bit is set every 62.5ms instead of once a second.
TAF
3
Transmit Align Frame. Set every 250s at the beginning of align frames.
Used to alert the host that the TAF and TNAF registers need to be
updated.
LOTC
2
Loss-of-Transmit Clock. Set when the TCLK pin has not transitioned for
one channel time (or 3.9ms).
RCMF
1
Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries;
continues to be set every 2ms on an arbitrary boundary if CRC4 is
disabled.
PRBSD
0
Pseudorandom Bit-Sequence Detect. When receive PRBS is enabled,
this bit is set when the 2
15 - 1 PRBS pattern is detected at RPOS and
RNEG. The PRBS pattern can be framed, unframed, or in a specific time
slot.
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