參數(shù)資料
型號(hào)： DS21Q59L
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 5/76頁(yè)
文件大?。?/td> 0K
描述： IC TXRX E1 QUAD 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 90
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 230mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： AIS 警報(bào)檢測(cè)器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測(cè)器，遠(yuǎn)程檢測(cè)器和發(fā)生器
DS21Q59 Quad E1 Transceiver
13 of 76
Table 4-G. Serial Port Control Pins
NAME
TYPE
FUNCTION
SDO
O
Serial Port Data Output. Data at this output can be updated on the rising or falling edge of SCLK.
SDI
I
Serial Port Data Input. Data at this input can be sampled on the rising or falling edge of SCLK.
ICES
I
Input Clock-Edge Select. ICES is used to select which SCLK clock edge samples data at SDI.
OCES
I
Output Clock-Edge Select. OCES is used to select which SCLK clock edge updates data at SDO.
SCLK
I
Serial Port Clock. SCLK is used to clock data into and out of the serial port.
Table 4-H. Line Interface Pins
NAME
TYPE
FUNCTION
MCLK
I
Master Clock Input. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is
used internally for both clock/data recovery and for jitter attenuation.
RTIP and
RRING
I
Receive Tip and Ring. RTIP and RRING are analog inputs for clock recovery circuitry. These pins connect
through a 1:1 step-up transformer to the E1 line. See Section 21 for details.
TTIP and
TRING
O
Transmit Tip and Ring. TTIP and TRING are analog line-driver outputs. These pins connect through a 1:2
step-up transformer to the E1 line. See Section 21 for details.
Table 4-I. Supply Pins
NAME
TYPE
FUNCTION
DVDD
Supply
Digital Positive Supply. 3.3V ±5%. Should be wired to the RVDD and TVDD pins.
RVDD
Supply
Receive Analog Positive Supply. 3.3V ±5%. Should be wired to the DVDD and TVDD pins.
TVDD
Supply
Transmit Analog Positive Supply. 3.3V ±5%. Should be wired to the RVDD and DVDD pins.
DVSS
Supply
Digital Signal Ground. 0V. Should be wired to the RVSS and TVSS pins.
RVSS
Supply
Receive Analog Signal Ground. 0V. Should be wired to DVSS and TVSS.
TVSS
Supply
Transmit Analog Signal Ground. 0V. Should be wired to DVSS and RVSS.
5. FUNCTIONAL DESCRIPTION
The analog AMI/HDB3 waveform off the E1 line is transformer-coupled into the DS21Q59’s RRING and RTIP pins.
The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the
receive framer, where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS21Q59
contains an active filter that reconstructs the analog-received signal for the nonlinear losses that occur in
transmission. The device has a usable receive sensitivity of 0dB to -43dB, which allows the device to operate on
cables over 2km in length. The receive framer locates FAS frame and CRC and CAS multiframe boundaries as well
as detects incoming alarms including carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the
receive elastic store can be enabled to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock, which is provided at the SYSCLK input. The clock applied at
the SYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The transmit framer is
independent of the receive framer in both the clock requirements and characteristics. The transmit formatter
provides the necessary frame/multiframe data overhead for E1 transmission.
Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125
ms frame,
there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots
are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1, time slot
1 is identical to channel 2, and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8.
Bit number 1, MSB, is transmitted first. Bit number 8, the LSB, is transmitted last. The term “l(fā)ocked” is used to refer
to two clock signals that are phase-locked or frequency-locked or derived from a common clock (i.e., an 8.192MHz
clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
相關(guān)PDF資料
PDF描述
VI-B5Z-IX-F2 CONVERTER MOD DC/DC 2V 30W
VI-B5Y-IY-F3 CONVERTER MOD DC/DC 3.3V 33W
VI-B5Y-IX-F1 CONVERTER MOD DC/DC 3.3V 49.5W
VI-B5Y-IW-F4 CONVERTER MOD DC/DC 3.3V 66W
DS2187S/T&R IC RECEIVE LINE INTERFACE 20SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q59L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q59LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q59LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21S07A 制造商:Maxim Integrated Products 功能描述:
DS21S07AE 功能描述:SCSI 接口集成電路 RoHS:否 制造商:Texas Instruments 工作電源電壓:2.7 V to 5.25 V 電源電流:13 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SSOP-36 封裝:Tube
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*