參數(shù)資料
型號： DS21Q59L
廠商： Maxim Integrated Products
文件頁數(shù)： 46/76頁
文件大?。?/td> 0K
描述： IC TXRX E1 QUAD 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 90
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 230mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠(yuǎn)程檢測器和發(fā)生器
DS21Q59 Quad E1 Transceiver
50 of 76
Figure 21-3. Transmit Waveform Template
21.3 Jitter Attenuators
The DS21Q59 contains an on-board clock and data jitter attenuator for each transceiver and a single, undedicated
“clock only” jitter attenuator. This undedicated jitter attenuator is shown in the block diagram (Figure 3-1) as the
alternate jitter attenuator.
21.3.1 Clock and Data Jitter Attenuators
The clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to buffer
depths of either 32 or 128 bits through the LICR. The 128-bit mode is used in applications where large excursions
of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the
attenuators are shown in Figure 21-5. The jitter attenuators can be placed in either the receive path or the transmit
path by appropriately setting or clearing the JAS bit in the LICR. Also, setting the DJA bit in the LICR can disable
the jitter attenuator (in effect, remove it). For the jitter attenuator to operate properly, a 2.048MHz clock (±50ppm)
must be applied at the MCLK pin. On-board circuitry adjusts either the recovered clock from the clock/data
recovery block or the clock applied at the TCLKI pin to create a smooth jitter-free clock that is used to clock data
out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter
attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or
28UIP-P (buffer depth is 32 bits), the DS21Q59 divides the internal nominal 32.768MHz clock by either 15 or 17
instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also
sets the jitter attenuator limit trip (JALT) bit in the receive information register (RIR.5).
0
-0.1
-0.2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
TIME (ns)
SCALED
AM
PLITUDE
50
100
150
200
250
-50
-100
-150
-200
-250
269ns
194ns
219ns
(in
75
W
sy
st
em
s,
1
.0
on
the
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2.
37
V
peak
in
120
W
sys
te
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s,
1.
0
on
the
s
ca
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=
3.
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pea
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G.703
TEMPLATE
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DS21Q59L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q59LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q59LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21S07A 制造商:Maxim Integrated Products 功能描述:
DS21S07AE 功能描述:SCSI 接口集成電路 RoHS:否 制造商:Texas Instruments 工作電源電壓:2.7 V to 5.25 V 電源電流:13 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SSOP-36 封裝:Tube
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