參數(shù)資料
型號: DS21Q59L
廠商: Maxim Integrated Products
文件頁數(shù): 37/76頁
文件大?。?/td> 0K
描述: IC TXRX E1 QUAD 3.3V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
功能: 收發(fā)器
接口: E1
電路數(shù): 4
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 230mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: AIS 警報檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠程檢測器和發(fā)生器
DS21Q59 Quad E1 Transceiver
42 of 76
17.
PER-CHANNEL LOOPBACK
The DS21Q59 has per-channel loopback capability that can operate in one of two modes: remote per-channel
loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are
looped back. In remote per-channel loopback mode, PCLB1/2/3/4 determine which channels (if any) in the transmit
direction should be replaced with the data from the receiver or, in other words, off the E1 line. In local per-channel
loopback mode, PCLB1/2/3/4 determine which channels (if any) in the receive direction should be replaced with the
data from the transmit. If either mode is enabled, transmit and receive clocks and frame syncs must be
synchronized. There are no restrictions on which channels can be looped back or on how many channels can be
looped back.
Register Name:
PCLB1, PCLB2, PCLB3, PCLB4
Register Description:
Per-Channel Loopback Registers
Register Address:
2B Hex, 2C Hex, 2D Hex, 2E Hex
Bit #
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
Name
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
NAME
BIT
FUNCTION
CH1 to CH32
PCLB1.0 to 4.7
Per-Channel Loopback Control Bits
0 = do not loopback this channel
1 = loopback this channel
18.
ELASTIC STORE OPERATION
The DS21Q59 contains a two-frame (512 bits) elastic store for the receive direction. The elastic store is used to
absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not
frequency locked) backplane clock that can be 2.048MHz for normal operation or 4.096MHz, 8.192MHz, or
16.384MHz when using the IBO function. The elastic store contains full controlled slip capability.
If the receive elastic store is enabled (RCR.4 = 1), the user must provide a 2.048MHz clock to the SYSCLK pin. If
the IBO function is enabled, a 4.096MHz, 8.192MHz, or 16.384MHz clock must be provided at the SYSCLK pin.
The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR.5 = 1) or having the
RSYNC pin provide a pulse on frame/multiframe boundaries (RCR.5 = 0). If the user wishes to obtain pulses at the
frame boundary, RCR1.6 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary,
RCR1.6 must be set to 1. If the elastic store is enabled, either CAS (RCR.7 = 0) or CRC4 (RCR.7 = 1) multiframe
boundaries are indicated through the RSYNC output. See Section 24 for timing details. If the 512-bit elastic buffer
either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of data (256 bits) is repeated at
RSER, and the SR1.4 and RIR.3 bits are set to 1. If the buffer fills, a full frame of data is deleted, and the SR1.4
and RIR.4 bits are set to 1.
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