參數(shù)資料
型號: DS26324DK
廠商: Maxim Integrated Products
文件頁數(shù): 28/120頁
文件大?。?/td> 0K
描述: KIT DESIGN FOR G549DS26324
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: G549DS26324
已供物品: 板,線纜,電源
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
15 of 120
NAME
PIN
TYPE
FUNCTION
D7/AD7
N3
I/O,
tri-state
Data Bus 7–0. In nonmultiplexed host mode, these pins are the
bidirectional data bus.
Address/Data Bus 7–0. In multiplexed host mode, these pins are the
bidirectional address/data bus. Note: AD7 and AD6 do not carry
address information.
In serial host mode, these pins should be grounded.
D6/AD6
P3
D5/AD5
M4
D4/AD4
L5
D3/AD3
K7
D2/AD2
P4
D1/AD1
M5
D0/AD0
L6
A5/BSWP
E4
I
Address 5. In the host nonmultiplexed mode, this is the most
significant bit of the address bus.
Bit Swap. In serial host mode, this bit defines the serial data position
to be MSB first when low and LSB first when high.
In multiplexed host mode, this pin should be grounded.
A4
C4
I
Address Bus 4–0. These five pins are address pins in the parallel
host mode.
In serial host mode and multiplexed host mode, these pins should be
grounded.
A3
H5
A2
G3
A1
H3
A0
N10
OE
R12
I
Output Enable. If this pin is pulled low all the transmitters outputs
(TTIP and TRING) are high impedance. If pulled high all the
transmitters are enabled when the associated output enable OE bit is
set. If TST.RHPMC is set, the OE pin is granted control of the
receiver internal termination. When OE is low, receiver internal
termination will be high impedance. When OE is high, receiver
termination will be enabled. The receiver can still monitor incoming
signals even when termination is in high impedance.
CLKE/MUX
T14
I
Clock Edge. If CLKE is high, SDO is clocked out on falling edge of
SCLK and if low SDO is on rising edge of SCLK.
Multiplexed/Nonmultiplexed Select Pin. When in parallel port
mode, this pin is used to select multiplexed address and data
operation or separate address and data. When mux is a high
multiplexed address and data is used and when mux is low
nonmultiplexed is used.
JTAG
TRSTB
E15
I,
pullup
JTAG Test Port Reset. This pin if low will reset the JTAG port. If not
used it can be left unconnected.
TMS
B13
I,
pullup
JTAG Test Mode Select. This pin is clocked on the rising edge of
TCK and is used to control the JTAG selection between scan and
Test Machine control.
TCK
D14
I
JTAG Test Clock. The data TDI and TMS are clocked on rising edge
of TCK and TDO is clocked out on the falling edge of TCK.
TDO
A15
O,
high-Z
JTAG Test Data Out. This is the serial output of the JTAG port. The
data is clocked out on the falling edge of TCK.
TDI
B15
I,
pullup
Test Data Input. This pin input is the serial data of the JTAG Test.
The data on TDI is clocked on the rising edge of TCK. This pin can be
left unconnected.
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DS26324GA2+ 功能描述:電信集成電路 RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
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