參數(shù)資料
型號(hào): DS26324DK
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 74/120頁(yè)
文件大?。?/td> 0K
描述: KIT DESIGN FOR G549DS26324
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: G549DS26324
已供物品: 板,線纜,電源
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DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
57 of 120
Register Address (LIUs 9–16):
2Fh
Bit #
7
6
5
4
3
2
1
0
Name
RIMPMS
AISEL
SCPD
CODE
JADS
CALEN
JAPS
JAE
Default
0
Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, the fully internal receive impedance
matching mode is selected, so RTIP and RRING require no external resistor. If this bit is set, the receiver line
transformer must be a 1:1 turns ratio and the RTR bit set. When reset and TS.RIMPON = 1, partially internal
receive impedance matching mode is selected and an external resistor is required to terminate the receive line.
This external resistor will be adjusted internally to the correct termination value.
Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the system side upon detecting
LOS for each channel. The individual LIU register IAISEL settings will be ignored when this bit is set. When reset,
the IAISEL register will have control.
Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the short-circuit protection is disabled for all the
transmitters. The individual LIU register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD
register will have control.
Bit 4: Code (CODE). If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored
when this bit is set. If reset, the LCS register will have control.
Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The
settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control.
Bit 2: Calibrate Receive Impedance Match (CALEN). This bit must be set to enable calibration of the receive
termination. If this bit is set and a 16k
resistor is on the RESREF pin, then a low-to-high transition on the CRIMP
bit will initiate a calibration cycle for the receive internal termination. The user should wait at least 5
s before
setting the CRIMP bit.
Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set, the jitter attenuator will be in the
receive path for each channel. The individual LIU register IJAPS settings will be ignored when this bit is set. When
reset, the IJAPS register will have control.
Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The settings in the IJAE
register will be ignored if this register is set. If reset, the IJAE register will have control.
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