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參數(shù)資料
| 型號(hào)： | DS26324GN+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 107/120頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V 256-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 16/16 |
| 規(guī)程： | LIN |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSBGA（17x17） |
| 包裝： | 帶卷 (TR) |
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DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
87 of 120
Register Name:
TEICR
Register Description:
Transmit Error Insertion Control Register
Register Address (LIUs 1–8):
08h
Register Address (LIUs 9–16):
28h
Bit #
7
6
5
4
3
2
1
0
Name
—
TEIR2
TEIR1
TEIR0
BEI
TSEI
MEIMS
Default
0
Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]). These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10
n bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value
of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A
TEIR[2:0] value of 2 result in every 100th bit being inverted. Error insertion starts when this register is written to
with a TEIR[2:0] value that is nonzero. If this register is written to during the middle of an error insertion process,
the new error rate will be started after the next error is inserted.
Bit 2: Bit Error Insertion Enable (BEI). When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be
inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause a bit error to be inserted.
Register Name:
BSR
Register Description:
BERT Status
Register Address (LIUs 1–8):
0Ch
Register Address (LIUs 9–16):
2Ch
Bit #
7
6
5
4
3
2
1
0
Name
—
PMS
—
BEC
OOS
Default
0
Bit 3: Performance Monitoring Update Status (PMS). This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS is
asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM=1) goes low.
Bit 1: Bit Error Count (BEC). When 0, the bit error count is zero. When 1, the bit error count is one or more.
Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26324N | 制造商:Maxim Integrated Products 功能描述:DS26324 X16 T1E1J1 LIU S-HAUL IND - Rail/Tube |
| DS26324-W | 功能描述:電信集成電路 RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS26334 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, 16-Channel, E1/T1/J1 Shortand Long-Haul Line Interface Unit |
| DS26334_07 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, 16-Channel, E1/T1/J1 Shortand Long-Haul Line Interface Unit |
| DS26334DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS26334 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
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