參數(shù)資料
型號: DS26324GN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 117/120頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 帶卷 (TR)
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
96 of 120
Table 7-2. ID Code Structure
MSB
LSB
Version
Contact Factory
Device ID
JEDEC
1
4 bits
16 bits
00010100001
1
Table 7-3. Device ID Codes
DEVICE
16-BIT ID
DS26324
003Ch
7.3
Test Registers
IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An
optional test register has been included with the DS26324 design. This test register is the Identification Register
and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
7.3.1
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells
and is n bits in length.
7.3.2
Bypass Register
This register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provide a
short path between TDI and TDO.
7.3.3
Identification Register
The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See Table
7-2 and Table 7-3 for more information about bit usage.
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