• <blockquote id="mkyht"></blockquote>

  • 參數(shù)資料
    型號(hào): DS26324GN+T&R
    廠商: Maxim Integrated Products
    文件頁數(shù): 50/120頁
    文件大?。?/td> 0K
    描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
    產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
    Obsolescence Mitigation Program
    標(biāo)準(zhǔn)包裝: 500
    類型: 線路接口裝置(LIU)
    驅(qū)動(dòng)器/接收器數(shù): 16/16
    規(guī)程: LIN
    電源電壓: 3.135 V ~ 3.465 V
    安裝類型: 表面貼裝
    封裝/外殼: 256-LBGA,CSBGA
    供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
    包裝: 帶卷 (TR)
    DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
    35 of 120
    5.9.2
    Configuration and Monitoring
    Set BTCR.BERTE = 1 to enable the BERT. The following tables show how to configure the on-board BERT to send
    and receive common patterns.
    Table 5-11. Pseudorandom Pattern Generation
    PATTERN TYPE
    BPCR REGISTER
    BERT.
    PCR
    BERT.
    SPR2
    BERT.
    SPR1
    BERT.CR
    PTF[4:0]
    (hex)
    PLF[4:0]
    (hex)
    PTS
    QRSS
    TPIC,
    RPIC
    2
    9-1 O.153 (511 type)
    04
    08
    0
    0x0408
    0xFFFF
    0
    2
    11-1 O.152 and O.153
    (2047 type)
    08
    0A
    0
    0x080A
    0xFFFF
    0
    2
    15-1 O.151
    0D
    0E
    0
    0x0D0E
    0xFFFF
    1
    2
    20-1 O.153
    10
    13
    0
    0x1013
    0xFFFF
    0
    2
    20-1 O.151 QRSS
    02
    13
    0
    1
    0x0253
    0xFFFF
    0
    2
    23-1 O.151
    11
    16
    0
    0x1116
    0xFFFF
    1
    Table 5-12. Repetitive Pattern Generation
    PATTERN TYPE
    BPCR REGISTER
    BERT.
    PCR
    BERT.
    SPR2
    BERT.
    SPR1
    PTF[4:0]
    (hex)
    PLF[4:0]
    (hex)
    PTS
    QRSS
    All Ones
    NA
    00
    1
    0
    0x0020
    0xFFFF
    All Zeros
    NA
    00
    1
    0
    0x0020
    0xFFFF
    0xFFFE
    Alternating Ones and Zeros
    NA
    01
    1
    0
    0x0021
    0xFFFF
    0xFFFE
    Double Alternating and Zeros
    NA
    03
    1
    0
    0x0023
    0xFFFF
    0xFFFC
    3 in 24
    NA
    17
    1
    0
    0x0037
    0xFF20
    0x0022
    1 in 16
    NA
    0F
    1
    0
    0x002F
    0xFFFF
    0x0001
    1 in 8
    NA
    07
    1
    0
    0x0027
    0xFFFF
    0xFF01
    1 in 4
    NA
    03
    1
    0
    0x0023
    0xFFFF
    0xFFF1
    After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
    transition on BCR.TNPL and BCR.RNPL
    Monitoring the BERT requires reading the BSR register, which contains the Bit Error Count (BEC) bit and the Out
    of Synchronization (OOS) bit. The BEC bit will be one when the bit error counter is one or more. The OOS will be
    one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it
    receives a minimum 6 bit errors within a 64-bit window. The Receive BERT Bit Count Register (RBCR) and the
    Receive BERT Bit Error Count Register (RBECR) will be updated upon the reception of a Performance Monitor
    Update signal (e.g., BCR.LPMU). This signal will update the registers with the values of the counters since the last
    update and will reset the counters.
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