參數(shù)資料
型號: DS26503L+
廠商: Maxim Integrated Products
文件頁數(shù): 105/122頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
T1 Mode
L2
L1
L0
APPLICATION
N (NOTE 1)
RETURN LOSS
Rt (NOTE 1)
0
DSX-1 (0 to 133 feet)/0dB CSU
1:2
N.M.
0
1
DSX-1 (133 to 266 feet)
1:2
N.M.
0
1
0
DSX-1 (266 to 399 feet)
1:2
N.M.
0
1
DSX-1 (399 to 533 feet)
1:2
N.M.
0
1
0
DSX-1 (533 to 655 feet)
1:2
N.M.
0
1
0
1
Reserved
1
0
Reserved
1
Reserved
Note 1: Transformer turns ratio.
N.M. = not meaningful
Register Name:
TLBC
Register Description:
Transmit Line Build-Out Control
Register Address:
34h
Bit #
7
6
5
4
3
2
1
0
Name
AGCE
GC5
GC4
GC3
GC2
GC1
GC0
Default
0
HW
Mode
0
Bit 0 to 5: Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting for the non-automatic gain
mode. Use the tables below for setting the recommended values. The LBO (line build-out) column refers to the value in the
L0–L2 bits in LIC1 (Line Interface Control 1) register.
NETWORK MODE
LB
GC5
GC4
GC3
GC2
GC1
GC0
0
1
0
1
0
1
0
1
0
1
2
0
1
0
1
0
3
1
0
4
1
0
1
5
1
0
1
6
0
1
0
1
7
1
0
1
0
1
0
1
0
1
0
1
2
0
1
0
1
0
1
3
0
1
0
1
0
4
1
0
1
0
5
1
0
6
0
1
0
T1, Impedance Match On
7
1
0
1
0
1
0
1
4
1
0
1
0
1
0
E1, Impedance Match Off
5
1
0
1
0
1
0
1
0
E1, Impedance Match On
1
0
1
0
1
0
T1, Impedance Match Off
Bit 6: Automatic Gain Control Enable (AGCE)
0 = use Transmit AGC, TLBC bits 0–5 are “don’t care”
1 = do not use Transmit AGC, TLBC bits 0–5 set nominal level
Bit 7: Unused, must be set = 0 for proper operation.
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