參數(shù)資料
型號: DS26503L+
廠商: Maxim Integrated Products
文件頁數(shù): 40/122頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: BITS 元件,多路復用器
PLL:
主要目的: T1/E1
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
24 of 122
MODE
PIN
TYPE
PARALLEL
PORT
SERIAL
PORT
HARDWARE
FUNCTION
18
O
TCLKO
Transmit Clock Output
19
O
TNEGO
Transmit Negative-Data Output
20
O
TPOSO
Transmit Positive-Data Output
21
I
TSER
Transmit Serial Data
23
I/O
TS
T1/E1 Mode: Transmit Frame/Multiframe Sync
25
O
RCLK
Receive Clock
26
O
RS
T1/E1 Mode: Receive Frame/Multiframe Boundary
27
N.C.
No Connect. This pin must be left open.
28
O
RSER
Receive Serial Data
29
O
RAIS
Receive Alarm Indication Signal
30
O
RLOF
Receive Loss of Frame
31
I
TCSS1
Parallel Port Mode: Unused, should be connected to
VSS.
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Transmit Clock Source Select 1
32
O
RLOS
Receive Loss Of Signal
33
I
JTMS
IEEE 1149.1 Test Mode Select
34
I
JTCLK
IEEE 1149.1 Test Clock Signal
35
I
JTRST
IEEE 1149.1 Test Reset
36
I
JTDI
IEEE 1149.1 Test Data Input
37
O
JTDO
IEEE 1149.1 Test Data Output
38
I
RVDD
Receive Analog Positive Supply
39
I
TSTRST
Test/Reset
40,
43, 45
I
RVSS
Receive Analog Signal Ground
41
I
RTIP
Receive Analog Tip Input
42
I
RRING
Receive Analog Ring Input
44
I
MCLK
Master Clock Input
46
I/O
INT
JACKS0
Parallel Port Mode: Active-Low Interrupt
Serial Port Mode: Active-Low Interrupt
Hardware Mode: Jitter Attenuator Clock Select 0
47
O
PLL_OUT
Transmit PLL (TX PLL) Clock Output
48
I
TMODE2
Parallel Port Mode: Unused, should be connected to
VSS.
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Transmit Mode Select 2
49
I
TMODE1
Parallel Port Mode: Unused, should be connected to
VSS.
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Transmit Mode Select 1
50
I
THZE
Transmit High-Impedance Enable
51
O
TTIP
Transmit Analog Tip Output
52
I
TVSS
Transmit Analog Signal Ground
53
I
TVDD
Transmit Analog Positive Supply
54
O
TRING
Transmit Analog Ring Output
55
I
BTS
HBE
Parallel Port Mode: Bus Type Select (Motorola/Intel)
Serial Port Mode: Unused, should be connected to VSS.
Hardware Mode: Receive and Transmit DB3/B8ZS
Enable
57
I
BIS0
Bus Interface Select Mode 0
59
I
BIS1
Bus Interface Select Mode 1
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