DS3150
22 of 28
FRAMER INTERFACE TIMING
(VDD = 3.3V
±5%, TA = 0°C to +70°C for DS3150Q/T, TA = -40°C to +85°C for DS3150QN/TN.) (Figure 3-1) PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 4)
22.4
(Note 5)
29.1
RCLK/TCLK Clock Period
t1
(Note 6)
19.3
ns
(Note 4)
9.0
11.2
13.4
(Note 5)
11.6
14.5
17.4
RCLK Clock High/Low Time
t2, t3
(Note 6)
7.7
9.6
11.5
ns
TCLK Clock High/Low Time
t2, t3
7
ns
TPOS/TNRZ, TNEG to TCLK
Setup Time
t4
2
ns
TPOS/TNRZ, TNEG Hold
Time
t5
2
ns
RCLK to RPOS/RNRZ Valid,
RNEG/RLCV Valid, State
Change on PRBS
t6
(Notes 7, 8)
2
6
ns
Note 4:
DS3 mode.
Note 5:
E3 mode.
Note 6:
STS-1 mode.
Note 7:
In normal mode, TPOS/TNRZ and TNEG are sampled on the rising edge of TCLK and RPOS/RNRZ and RNEG/RLCV are
updated on the falling edge of RCLK.
Note 8:
In inverted mode, TPOS/TNRZ and TNEG are sampled on the falling edge of TCLK and RPOS/RNRZ and RNEG/RLCV are
updated on the rising edge of RCLK.
Figure 3-1. Framer Interface Timing Diagram
RCLK (normal mode),
TCLK (inverted mode)
TPOS/TNRZ, TNEG
RPOS/RNRZ,
RNEG/RLCV, PRBS
t4
t5
t6
t1
t2
t3
TCLK (normal mode),
RCLK (inverted mode)