參數(shù)資料
型號： DS3154N+
廠商： Maxim Integrated Products
文件頁數(shù)： 24/61頁
文件大?。?/td> 0K
描述： IC LIU DS3/E3/STS-1 QD 144CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： IEEE 1149.1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-TECSBGA（13x13）
包裝： 管件
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
30 of 61
the JA must take its master clock from the MCLK pin. The clock and data recovery block also uses the selected
master clock.
The JA has a loop bandwidth of master_clock / 2,058,874 (see corner frequencies in Figure 9-1). The JA
attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
Figure 9-1. Jitter Attenuation/Jitter Transfer
10.
RESET LOGIC
There are four sources for reset: an internal power-on reset (POR) circuit, the reset pin
RST, the JTAG reset pin
JTRST, and the RST bit in each LIU’s global configuration register (GCR). The chip is divided into three zones for
reset: the digital logic, the analog circuits, and the JTAG logic. The digital logic includes the status and control
registers, the B3ZS/HDB3 encoder and decoder, the PRBS generator and detector, and the LOS detect logic. The
analog circuits include clock and data recovery, jitter attenuator, and transmit waveform generation. The JTAG
logic consists of the common boundary scan controller and the boundary scan cells at each pin.
The POR circuit resets the digital logic, analog circuits, and JTAG logic zones. The
RST pin resets the digital logic
and the analog circuits but not the JTAG logic. The
JTRST pin resets only the JTAG logic. Each LIU’s RST register
bit resets the digital logic for that LIU, including resetting the LIU’s registers to the default state (except for the RST
bit).
The POR signal and
RST pin require an active master clock source for the LIU to properly reset.
10
100
1k
10k
100k
1M
21.7Hz (DS3)
16.7Hz (E3)
25.2Hz (STS-1)
1k
-30
-20
-10
E3 [TBR24 (1997)]
FREQUENCY (Hz)
JITTER
AT
TENU
ATION
(dB)
0
DS3
[GR-499
(1995)]
CATEGORY I
DS315x TYPICAL RECEIVER
JITTER TRANSFER WITH JITTER
ATTENUATOR DISABLED
>150k
DS315x
DS3/E3/STS-1
MINIMUM
JITTER
ATTENUATION
WITH JITTER
ATTENUATOR
ENABLED
40Hz
DS3 [GR-253 (1999)]
CATEGORY I
27Hz
STS-1 [GR-253
(1999)]
CATEGORY II
40k 59.6k
DS3 [GR-499 (1999)]
CATEGORY II
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