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參數(shù)資料
| 型號： | DS3253DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEMO FOR DS3253 |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 主要目的： | 電信，線路接口單元（LIU） |
| 已用 IC / 零件： | DS3253 |
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DS3251/DS3252/DS3253/DS3254
27 of 71
Figure 8-1. Receiver Jitter Tolerance
9. TRANSMITTER
9.1 Transmit Clock
The clock applied at the TCLK input clocks in data on the TPOS/TDAT and TNEG pins. If the jitter attenuator is not
enabled in the transmit path, the signal on TCLK is the transmit line clock and must be transmission quality (i.e.,
±20ppm frequency accuracy and low jitter). If the jitter attenuator is enabled in the transmit path, the signal on
TCLK can be jittery and/or periodically gapped, but must still have an average frequency within
±20ppm of the
nominal line rate. When enabled in the transmit path, the jitter attenuator generates the transmit line clock from the
appropriate master clock.
The polarity of TCLK can be inverted to support glueless interfacing to a variety of neighboring components.
Normally data is sampled on the TPOS/TDAT and TNEG pins on the rising edge of TCLK. To sample data on the
falling edge of TCLK, pull the TCINV pin high (hardware mode) or set the TCINV configuration bit in the TCR
register (CPU bus mode).
9.2 Framer Interface Format and the B3ZS/HDB3 Encoder
Data to be transmitted can be input in either binary or bipolar format. To select the binary interface format, pull the
TBIN pin high (hardware mode) or set the TBIN configuration bit in the TCR register (CPU bus mode). In binary
format, the B3ZS/HBD3 encoder is enabled, and the data to be transmitted is sampled on the TDAT pin. The
TNEG pin is ignored in binary interface mode and should be wired low. In DS3 and STS-1 modes, the B3ZS/HDB3
encoder operates in the B3ZS mode. In E3 mode the encoder operates in HDB3 mode.
To select the bipolar interface format, pull the TBIN pin low (hardware mode) or clear the TBIN configuration bit in
the TCR register (CPU bus mode). In bipolar format, the B3ZS/HDB3 encoder is disabled and the data to be
transmitted is sampled on the TPOS and TNEG pins. Positive-polarity pulses are indicated by TPOS = 1, while
negative-polarity pulses are indicated by TNEG = 1.
9.3 Pattern Generation
The transmitter can generate several patterns internally, including unframed all ones (E3 AIS), 100100…, and DS3
AIS. See Figure 9-2 for the structure of the DS3 AIS signal. The TDSA and TDSB input pins (hardware mode) or
the TDSA and TDSB control bits in the GCR register (CPU bus mode) are used to select these patterns. Table 6-G
indicates the possible selections.
10
100
1k
10k
100k
1M
60k
22.3k
2.3k
669
0.1
1.0
10
300k
800k
300
30
0.1
0.15
0.3
10
5
1.5
E3 G.823
DS3 GR-499 Cat II
DS3 GR-499 Cat I
DS325x JITTER TOLERANCE
15
STS-1 GR253
FREQUENCY (Hz)
JITTER
TOLERANCE
(UI
P-
P
)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS3253N | 功能描述:網(wǎng)絡控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253N# | 功能描述:網(wǎng)絡控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253N+ | 功能描述:網(wǎng)絡控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253NA3 | 制造商:Maxim Integrated Products 功能描述:DS3253 REV A3 - Rail/Tube |
| DS3254 | 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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