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參數資料
型號: DS3253DK
廠商: Maxim Integrated Products
文件頁數: 44/71頁
文件大?。?/td> 0K
描述: KIT DEMO FOR DS3253
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS3253
DS3251/DS3252/DS3253/DS3254
49 of 71
Table 17-H. Parallel CPU Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 17-3 and Figure 17-4)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Setup Time for A[5:0] Valid to
CS Active (Notes 1, 2)
t1
0
ns
Setup Time for
CS Active to RD, WR, or DS Active
t2
0
ns
Delay Time from
RD or DS Active to D[7:0] Valid
t3
65
ns
Hold Time from
RD or WR or DS Inactive to CS Inactive
t4
0
ns
Delay from
CS or RD or DS Inactive to D[7:0] Invalid or Tri-
State (Note 3)
t5
2
20
ns
Wait Time from
WR or DS Active to Latch D[7:0]
t6
65
ns
D[7:0] Setup Time to
WR or DS Inactive
t7
10
ns
D[7:0] Hold Time from
WR or DS Inactive
t8
2
ns
A[5:0] Hold Time from
WR or RD or DS Inactive
t9
5
ns
RD, WR, or DS Inactive Time
t10
75
ns
Muxed Address Valid to ALE Falling (Note 4)
t11
10
ns
Muxed Address Hold Time (Note 4)
t12
10
ns
ALE Pulse Width (Note 4)
t13
30
ns
Setup Time for ALE High or Muxed Address Valid to
CS
Active (Note 4)
t14
0
ns
Note 1:
D[7:0] loaded with 50pF when tested as outputs.
Note 2:
If a gapped clock is applied on TCLK and local loopback is enabled, read cycle time must be extended by the length of the largest
TCLK gap.
Note 3:
Not tested during production test.
Note 4:
In nonmultiplexed bus applications (Figure 17-3), ALE should be wired high. In multiplexed bus applications (Figure 17-4), A[5:0]
should be wired to D[5:0] and the falling edge of ALE latches the address.
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