T
參數(shù)資料
型號: DS3510T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 13/17頁
文件大?。?/td> 0K
描述: IC I2C GAMMA/VCOM BUFF 48-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
應(yīng)用: TFT-LCD 面板:伽瑪緩沖器,VCOM 驅(qū)動器
輸出類型: 滿擺幅
電路數(shù): 10
電流 - 電源: 6.7mA
電流 - 輸出 / 通道: 4mA
電壓 - 電源,單路/雙路(±): 9 V ~ 15 V
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
EEPROM Write Cycles
TA = +70°C
50,000
Writes
EEPROM Write Cycles
TA = +25°C
200,000
Writes
DS3510
I2C Gamma and VCOM Buffer with EEPROM
_______________________________________________________________________________________
5
Note 1:
All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are
negative.
Note 2:
IDD supply current is specified with VDD = 15.0V and no load on VCOM or GM1–10 outputs.
Note 3:
Specified with the VCOM and gamma bias currents set to 100%.
Note 4:
ICC is specified with the following conditions: SCL = 400kHz, SDA = VCC = 5.5V, and VCOM and GM1–10 floating.
Note 5:
ICCQ is specified with the following conditions: SCL = SDA = VCC = 5.5V, and VCOM and GM1–10 floating.
Note 6:
IDDQ is specified with the following conditions: SCL = SDA = VCC = 5.5V and VCOM and GM1–10 floating.
Note 7:
Guaranteed by design.
Note 8:
Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected
value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting.
INL = [V(RW)i - (V(RW)0]/LSB(measured) - i, for i = 0...255.
Note 9:
Differential nonlinearity is the deviation of the step size change between two LSB settings from the expected step size. The
expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
DNL = [V(RW)i+1 - (V(RW)i]/LSB(measured) - 1, for i = 0...254.
Note 10: Tested at VRL = VRH = 6.5V/7.5V/8.5V, GLL = GLM = 0.5V/6.5V/8.5V/14.5V, GHM = GHH = 0.5V/6.5V/8.5V/14.5V.
Note 11: EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected.
Note 12: Rising transition from 5V to 10V; falling transition from 10V to 5V.
Note 13: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C
standard mode timing.
Note 14: CB—total capacitance of one bus line in picofarads.
Note 15: EEPROM write time begins after a STOP condition occurs.
Note 16: Pulses narrower than max are suppressed.
VCOM
2
Ω
100nF
S0/S1
LD
VCOM
VIH
VIL
tSU
tHD
tSET-V
0.1% SETTLED
Figure 1. VCOM Settling Timing Diagram
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