參數(shù)資料
型號: DS87C530-QCL
英文描述: EPROM MICRO WITH REAL TIME CLOCK
中文描述: 微型存儲器與實時時鐘
文件頁數(shù): 12/40頁
文件大?。?/td> 435K
代理商: DS87C530-QCL
DS87C530
022197 12/40
ROM MEMORY MAP
Figure 4
ON CHIP
OFF CHIP
OFF CHIP
EA=1
EA=0
64K
16K
64K
FFFFh
0000h
FFFFh
0000h
3FFFh
DEFAULT = 16K BYTES
ROM SIZE IGNORED
USER
SELECTABLE
DATA MEMORY ACCESS
Unlike many 8051 derivatives, the DS87C530 contains
on–chip data memory. It also contains the standard 256
bytes of RAM accessed by direct instructions. These
areas are separate. The MOVX instruction accesses
the on–chip data memory. Although physically on–chip,
software treats this area as though it was located off–
chip. The 1KB of SRAM is between address 0000h and
03FFh.
Access to the on–chip data RAM is optional under soft-
ware control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX
instruction that uses this area will go to the on–chip RAM
while enabled. MOVX addresses greater than 03FFh
automatically go to external memory through Ports 0
and 2.
When disabled, the 1KB memory area is transparent to
the system memory map. Any MOVX directed to the
space between 0000h and FFFFh goes to the expanded
bus on Ports 0 and 2. This also is the default condition.
This default allows the DS87C530 to drop into an exist-
ing system that uses these addresses for other hard-
ware and still have full compatibility.
The on–chip data area is software selectable using two
bits in the Power Management Register at location C4h.
This selection is dynamically programmable. Thus
access to the on–chip area becomes transparent to
reach off–chip devices at the same addresses. The con-
trol bits are DME1 (PMR.1) and DME0 (PMR.0). They
have the following operation:
DATA MEMORY ACCESS CONTROL
Table 3
DME1
DME0
DATA MEMORY ADDRESS
MEMORY FUNCTION
0
0
0000h – FFFFh
External Data Memory *Default condition
0
1
0000h – 03FFh
0400h – FFFFh
Internal SRAM Data Memory
External Data Memory
1
0
Reserved
Reserved
1
1
0000h – 03FFh
0400h – FFFBh
FFFCh
FFFDh–FFFh
Internal SRAM Data Memory
Reserved – no external access
Read access to the status of lock bits
Reserved – no external access
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of the security lock
bits LB2–LB0. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.
These status bits allow software to verify that the part has been locked before running if desired. The bits are read only.
Note: After internal MOVX SRAM has been initialized, changing bits DEM0/1 will have no affect on the contents of the
SRAM.
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