參數(shù)資料
型號(hào)： DS87C530-QCL
英文描述： EPROM MICRO WITH REAL TIME CLOCK
中文描述： 微型存儲(chǔ)器與實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù)： 21/40頁(yè)
文件大小： 435K
代理商： DS87C530-QCL
DS87C530
022197 21/40
TIMER RATE CONTROL
There is one important difference between the
DS87C530 and 8051 regarding timers. The original
8051 used 12 clocks per cycle for timers as well as for
machine cycles. The DS87C530 architecture normally
uses 4 clocks per machine cycle. However, in the area
of timers and serial ports, the DS87C530 will default to
12 clocks per cycle on reset. This allows existing code
with real–time dependencies such as baud rates to
operate properly.
If an application needs higher speed timers or serial
baud rates, the user can select individual timers to run at
the 4 clock rate. The Clock Control register (CKCON;
8Eh) determines these timer speeds. When the relevant
CKCON bit is a logic 1, the DS87C530 uses 4 clocks per
cycle to generate timer speeds. When the bit is a 0, the
DS87C530 uses 12 clocks for timer speeds. The reset
condition is a 0. CKCON.5 selects the speed of Timer 2.
CKCON.4 selects Timer 1 and CKCON.3 selects Timer
0. Unless a user desires very fast timing, it is unneces-
sary to alter these bits. Note that the timer controls are
independent.
POWER–FAIL RESET
The DS87C530 uses a precision band–gap voltage ref-
erence to decide if V
CC
is out of tolerance. While power-
ing up, the internal monitor circuit maintains a reset
state until V
CC
rises above the V
RST
level. Once above
this level, the monitor enables the crystal oscillator and
counts 65536 clocks. It then exits the reset state. This
power–on reset (POR) interval allows time for the oscil-
lator to stabilize.
A system needs no external components to generate a
power–related reset. Anytime V
CC
drops below V
RST
,
as in power–failure or a power drop, the monitor will gen-
erate and hold a reset. It occurs automatically, needing
no action from the software. Refer to the Electrical
Specifications for the exact value of V
RST
.
POWER–FAIL INTERRUPT
The voltage reference that sets a precise reset thresh-
old also generates an optional early warning Power–fail
Interrupt (PFI). When enabled by software, the proces-
sor will vector to program memory address 0033h if V
CC
drops below V
PFW
. PFI has the highest priority. The PFI
enable is in the Watchdog Control SFR (WDCON –
D8h). Setting WDCON.5 to a logic 1 will enable the PFI.
Application software can also read the PFI flag at
WDCON.4. A PFI condition sets this bit to a 1. The flag is
independent of the interrupt enable and software must
manually clear it. If the PFI is enabled and the band–gap
select bit (BGS) is set, a PFI will bring the device out of
Stop mode.
WATCHDOG TIMER
To prevent software from losing control, the DS87C530
includes a programmable Watchdog Timer. The Watch-
dog is a free running timer that sets a flag if allowed to
reach a preselected time–out. It can be (re)started by
software.
A typical application is to select the flag as a reset
source. When the Watchdog times out, it sets its flag
which generates reset. Software must restart the timer
before it reaches its time–out or the processor is reset.
Software can select one of four time–out values. Then, it
restarts the timer and enables the reset function. After
enabling the reset function, software must then restart
the timer before its expiration or hardware will reset the
CPU. Both the Watchdog Reset Enable and the Watch-
dog Restart control bits are protected by a “Timed
Access” circuit. This prevents errant software from acci-
dentally clearing the Watchdog. Time–out values are
precise since they are a function of the crystal frequency
as shown below in Table 8. For reference, the time peri-
ods at 33 MHz also are shown.
The Watchdog also provides a useful option for systems
that do not require a reset circuit. It will set an interrupt
flag 512 clocks before setting the reset flag. Software
can optionally enable this interrupt source. The interrupt
is independent of the reset. A common use of the inter-
rupt is during debug, to show developers where the
Watchdog times out. This indicates where the Watch-
dog must be restarted by software. The interrupt also
can serve as a convenient time–base generator or can
wake–up the processor from power saving modes.
The Watchdog function is controlled by the Clock Con-
trol (CKCON – 8Eh), Watchdog Control (WDCON –
D8h), and Extended Interrupt Enable (EIE – E8h) SFRs.
CKCON.7 and CKCON.6 are WD1 and WD0 respec-
tively and they select the Watchdog time–out period as
shown in Table 8.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS87C530-QCL+ 功能描述:8位微控制器 -MCU EPROM MCU w/RTC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
DS87C530-QEL 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS87C530-QNL 功能描述:8位微控制器 -MCU EPROM MCU w/RTC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
DS87C530-QNL+ 功能描述:8位微控制器 -MCU EPROM MCU w/RTC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
DS87C530Z+ECL 制造商:Maxim Integrated Products 功能描述:MICRO OTP RTC 33MHZ 52P TQFP PB-FRR - Trays
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