DS87C530
022197 13/40
STRETCH MEMORY CYCLE
The DS87C530 allows software to adjust the speed of
off–chip data memory access. The micro is capable of
performing the MOVX in as few as two instruction
cycles. The on–chip SRAM uses this speed and any
MOVX instruction directed internally uses two cycles.
However, the time can be stretched for interface to
external devices. This allows access to both fast
memory and slow memory or peripherals with no glue
logic. Even in high–speed systems, it may not be neces-
sary or desirable to perform off–chip data memory
access at full speed. In addition, there are a variety of
memory mapped peripherals such as LCDs or UARTs
that are slow.
The Stretch MOVX is controlled by the Clock Control
Register at SFR location 8Eh as described below. It
allows the user to select a Stretch value between zero
and seven. A Stretch of zero will result in a two machine
cycle MOVX. A Stretch of seven will result in a MOVX of
nine machine cycles. Software can dynamically change
this value depending on the particular memory or
peripheral.
On reset, the Stretch value will default to a one resulting
in a three cycle MOVX for any external access. There-
fore, off–chip RAM access is not at full speed. This is a
convenience to existing designs that may not have fast
RAM in place. Internal SRAM access is always at full
speed regardless of the Stretch setting. When desiring
maximum speed, software should select a Stretch value
of zero. When using very slow RAM or peripherals,
select a larger Stretch value. Note that this affects data
memory only and the only way to slow program memory
(ROM) access is to use a slower crystal.
Using a Stretch value between one and seven causes
the microcontroller to stretch the read/write strobe and
all related timing. Also, setup and hold times are
increased by 1 clock when using any Stretch greater
than 0. This results in a wider read/write strobe and
relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the vari-
able speed MOVX is in the Electrical Specifications.
Table 4 shows the resulting strobe widths for each
Stretch value. The memory Stretch uses the Clock Con-
trol Special Function Register at SFR location 8Eh. The
Stretch value is selected using bits CKCON.2–0. In the
table, these bits are referred to as M2 through M0. The
first Stretch (default) allows the use of common 120 ns
RAMs without dramatically lengthening the memory
access.
DATA MEMORY CYCLE STRETCH VALUES
Table 4
CKCON.2–0
M2
M1
M0
MEMORY CYCLES
RD OR WR STROBE
WIDTH IN CLOCKS
STROBE WIDTH TIME
@ 33 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 (forced internal)
3 (default external)
4
5
6
7
8
9
2
4
8
12
16
20
24
28
60 ns
121 ns
242 ns
364 ns
485 ns
606 ns
727 ns
848 ns
DUAL DATA POINTER
The timing of block moves of data memory is faster
using the DS87C530 Dual Data Pointer (DPTR). The
standard 8051 DPTR is a 16–bit value that is used to
address off–chip data RAM or peripherals. In the
DS87C530, the standard data pointer is called DPTR,
located at SFR addresses 82h and 83h. These are the
standard locations. Using DPTR requires no modifica-
tion of standard code. The new DPTR at SFR 84h and
85h is called DPTR1. The DPTR Select bit (DPS)
chooses the active pointer. Its location is the lsb of the
SFR location 86h. No other bits in register 86h have any
effect and are 0. The user switches between data point-
ers by toggling the lsb of register 86h. The increment
(INC) instruction is the fastest way to accomplish this.
All DPTR–related instructions use the currently
selected DPTR for any activity. Therefore it takes only
one instruction to switch from a source to a destination
address. Using the Dual Data Pointer saves code from
needing to save source and destination addresses
when doing a block move. The software simply switches
between DPTR and 1 once software loads them. The
relevant register locations are as follows.