參數(shù)資料
型號(hào)： DS87C550-QNL
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 22/49頁(yè)
文件大?。?/td> 0K
描述： IC MCU EPROM ADC/PWM HS 68-PLCC
標(biāo)準(zhǔn)包裝： 18
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，PWM，WDT
輸入/輸出數(shù)： 55
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
29 of 49
The watchdog timer uses the internal system clock as a time base so its timeout periods are very accurate.
From the table, it can be seen that for a 33MHz crystal frequency, the watchdog timer is capable of
producing timeout periods from 3.97 ms (217 * 1/33MHz) to over two seconds (2.034 = 226 * 1/33MHz)
with the default setting of CD1:0 (=10). This wide variation in timeout periods allows very flexible
system implementation.
In a typical initialization, the user selects one of the possible counter values to determine the timeout.
Once the counter chain has completed a full count, hardware will set the interrupt flag
(WDIF=WDCON.3). There is no hardware support for a watchdog interrupt, but this flag may be polled
to determine if the timeout period has been completed. Regardless of whether the software makes use of
this flag, there are then 512 clocks left until the reset flag (WTRF=WDCON.2) is set. Software can
enable (1) or disable (0) the reset using the Enable Watchdog Reset (EWT=WDCON.1) bit. Note that the
watchdog is a free running timer and does not require an enable.
POWER-FAIL RESET
The DS87C550 incorporates an internal precision band-gap voltage reference which, when coupled with
a comparator circuit, provides a full power-on and power-fail reset function. This circuit monitors the
processor’s incoming power supply voltage (VCC) and holds the processor in reset while VCC is out of
tolerance. Once VCC has risen above VRST, the DS87C550 will restart the oscillator for the external crystal
and count 65,536 clock cycles before program execution begins at location 0000h. This power supply
monitor will also invoke the reset state when VCC drops below the threshold condition. This reset
condition will remain while power is below the minimum voltage level. When power exceeds the reset
threshold, a full power-on reset will be performed. In this way, this internal voltage monitoring circuitry
handles both power-up and power down conditions without the need for additional external components.
The processor exits the reset condition automatically once VCC meets VRST. This helps the system
maintain reliable operation by only permitting processor operation when its supply voltage is in a known
good state. Software can determine that a Power-On Reset has occurred by checking the Power-On Reset
flag (POR=WDCON.6). Software should clear the POR bit after reading it.
The Reset pin of the DS87C550 is both an input and an output. When the processor is being held in reset
by the power-fail detection circuitry, the reset pin will be actively pulled high by the processor, and can
therefore be used as an input to other external devices.
POWER-FAIL INTERRUPT
The band-gap voltage reference that sets a precise reset threshold also generates an optional early warning
Power-fail Interrupt (PFI). When enabled by software, the processor will vector to ROM address 0033h if
VCC drops below VPFW. PFI has the highest priority. The PFI enable is in the Watchdog Control SFR
(EPFI=WDCON.5). Setting this bit to a logic 1 will enable the PFI. Application software can also read
the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the interrupt
enable and software must manually clear it.
INTERRUPTS
The DS87C550 provides 16 interrupt sources with three priority levels. The Power-fail Interrupt (PFI) has
the highest priority. All interrupts, with the exception of the Power-fail Interrupt, are controlled by a
series combination of individual enable bits and a global interrupt enable EA (IE.7). Setting EA to a 1
allows individual interrupts to be enabled. Clearing EA disables all interrupts regardless of their
individual enable settings.
相關(guān)PDF資料
PDF描述
MC908LK24CPBE IC MCU 8BIT 64-LQFP
1588908-1 JR FRRL KIT, PC 126 SEALED
1278530-1 RETAINING CLIP, 1X4 BACKPLANE
1544551-1 CONNECTOR 5V 6.35
492578-1 DUST COVER,DAUGHTER CARD HSG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS88 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
DS8800 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Voltage Level Translator
DS8800H 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Voltage Level Translator
DS8800H/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TTL-to-MOS Translator
DS8802J/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOS-to-TTL Translator
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*