參數(shù)資料
型號(hào)： DS87C550-QNL
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 9/49頁(yè)
文件大?。?/td> 0K
描述： IC MCU EPROM ADC/PWM HS 68-PLCC
標(biāo)準(zhǔn)包裝： 18
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，PWM，WDT
輸入/輸出數(shù)： 55
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
17 of 49
oscillator-fail detect circuit, the processor will be forced to a known state (i.e., reset) even if the oscillator
stops.
The oscillator-fail detect circuitry is enabled by software setting the enable bit OFDE (PCON.4) to a 1.
There is an oscillator-fail detect flag, OFDF (PCON.5), that is set to a 1 by the hardware when it detects
an oscillator failure. The processor will be forced into a reset state when this occurs if enabled by OFDE.
The oscillator-fail detect flag can only be cleared to a 0 by a power-up reset or by software. It should be
noted that the oscillator-fail detect circuitry is not disabled by entering Stop mode. Therefore, the user
must ensure that this feature is disabled before entering Stop mode.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. Normally, during default operation, the DS87C550
uses 4 clocks per machine cycle. Thus the instruction cycle (machine cycle clock) rate is clock/4. At
33MHz crystal speed, the instruction cycle speed is 8.25MHz. In PMM the microcontroller operates, but
from an internally divided version of the clock source. This creates a lower power state without external
components. As shown in Figure 3, the system clock may be selected to use the crystal (or external
oscillator) frequency divided by 256. This produces a machine cycle that consists of the crystal frequency
divided by 1024, which is considered Power Management Mode (PMM). With the processor executing
instructions at this much lower rate, a significant amount of power is saved.
Software is the only mechanism to invoke the PMM. Table 6 illustrates the instruction cycle rate in PMM
for several common crystal frequencies. Since power consumption is a direct function of operating speed,
PMM runs very slowly and provides the lowest power consumption without stopping the CPU. This is
illustrated in Table 7.
MACHINE CYCLE RATE Table 6
Full Operation
PMM
Crystal Speed
(4 clocks per machine cycle)
(1024 clocks per machine cycle)
11.0592MHz
2.765MHz
10.8 kHz
16MHz
4.0MHz
15.6 kHz
25MHz
6.25MHz
24.4 kHz
33MHz
8.25MHz
32.2 kHz
OPERATING CURRENT ESTIMATES IN PMM Table 7
FULL OPERATION (mA)
PMM (mA)
CRYSTAL
SPEED (MHz)
(4 CLOCKS PER
MACHINE CYCLE)
(1024 CLOCKS PER
MACHINE CYCLE)
11.0592
13.1
4.8
16
17.2
5.6
25
25.7
7.0
33
32.8
8.2
Note that PMM provides a lower power condition than Idle mode. This is because in Idle, all clocked
functions such as timers run at a rate of crystal divided by 4. Since wakeup from PMM is as fast as or
faster than wakeup from Idle, and since PMM allows the CPU to continue to execute instructions (even if
doing NOPs), there is little reason to use Idle in new designs.
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