參數(shù)資料
型號: DSD1792ADBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 24-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁數(shù): 21/57頁
文件大?。?/td> 634K
代理商: DSD1792ADBG4
DSD1792A
SLES106B FEBRUARY 2004 REVISED NOVEMBER 2006
www.ti.com
28
ZFGx: Zero-Detection Flag
Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback.
Default value: 00
ZFGx = 0
Not zero
ZFGx = 1
Zero detected
When the DSD1792A detects that audio input data is continuously zero, the ZFGx bit is set to 1 for the corresponding
channel(s).
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 23
R
0
1
0
1
RSV
ID4
ID3
ID2
ID1
ID0
R: Read Mode Select
Value is always 1, specifying the readback mode.
ID[4:0]: Device ID
The ID[4:0] bits show a device ID in the TDMCA mode.
TYPICAL CONNECTION DIAGRAM IN PCM MODE
DSD1792A
PDATA
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
PBCK
SCK
DGND
VDD
MS
MDI
MC
MDO
RST
AGND2
IOUTR–
VCC1
VCOML
VCOMR
IREF
IOUTR+
AGND3R
AGND1
+
DSDL
1
2
3
4
DSDR
DBCK
PLRCK
28
27
26
25
VCC2L
AGND3L
IOUTL–
IOUTL+
DSD
Audio Data
Source
VOUT
L-Channel
5 V
VCC2R
0.1
F
Controller
10
F
3.3 V
PCM
Audio Data
Source
0.1
F
10
F
Cf
Rf
Differential
to
Single
Converter
With
Low-Pass
Filter
+
47
F
47
F
5 V
10
F
10 k
+
Cf
Rf
+
VOUT
R-Channel
Cf
Rf
Differential
to
Single
Converter
With
Low-Pass
Filter
+
Cf
Rf
0.1
F
10
F
5 V
+
Figure 32. Typical Application Circuit for Standard PCM Audio Operation
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