參數(shù)資料
型號(hào)： DSD1792ADBG4
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： DAC
英文描述： SERIAL INPUT LOADING, 24-BIT DAC, PDSO28
封裝： GREEN, PLASTIC, TSSOP-28
文件頁(yè)數(shù)： 36/57頁(yè)
文件大小： 634K
代理商： DSD1792ADBG4
DSD1792A
SLES106B FEBRUARY 2004 REVISED NOVEMBER 2006
www.ti.com
41
DSD MODE CONFIGURATION AND FUNCTION CONTROLS
Configuration for the DSD Interface Mode
DSD = 1 (Register 20, B5)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
1
0
–
Register 17
R/W
0
1
0
1
–
Register 18
R/W
0
1
0
1
0
–
DMF1
DMF0
–
Register 19
R/W
0
1
0
1
REV
–
OPE
–
Register 20
R/W
0
1
0
1
0
–
SRST
1
–
MONO
CHSL
OS1
OS0
Register 21
R
0
1
0
1
0
1
–
DZ1
DZ0
–
Register 22
R
0
1
0
1
0
–
ZFGR
ZFGL
NOTE:
–: Function is disabled. No operation even if data bit is set
DMF[1:0]: Analog FIR Performance Selection
Default value: 00
DMF[1:0]
Analog-FIR Performance Select
00
FIR-1 (default)
01
FIR-2
10
FIR-3
11
FIR-4
Plots for the four analog FIR filter responses are shown in the TYPICAL PERFORMANCE CURVES section
of this data sheet.
OS[1:0]: Analog-FIR Operation-Speed Selection
Default value: 00
OS[1:0]
Operation Speed Select
00
fDBCK (default)
01
fDBCK/2
10
Reserved
11
fDBCK/4
The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set
before setting the DSD bit to 1.
Requirements for System Clock
The bit clock (BCK) for the DSD mode is required at pin 3 of the DSD1792A. The frequency of the bit clock can
be N times the sampling frequency. Generally, N is 64 in DSD applications.
The interface timing between the bit clock and DATAL and DATAR is required to meet the same setup- and
hold-time specifications as shown for the audio interface timing in Figure 42.
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DSD1792DBG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類(lèi)型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
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