參數(shù)資料
型號: DSD1792ADBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 24-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁數(shù): 7/57頁
文件大?。?/td> 634K
代理商: DSD1792ADBG4
DSD1792A
SLES106B FEBRUARY 2004 REVISED NOVEMBER 2006
www.ti.com
15
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The DSD1792A requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The DSD1792A has a system clock detection circuit that
automatically senses if the system clock is operating between 128 fS and 768 fS. Table 1 shows examples of system clock
frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 fS,
the system clock frequency is over 256 fS.
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators is an
excellent choice for providing the DSD1792A system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
SAMPLING FREQUENCY
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
32 kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1 kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
49.152
73.728
192 kHz
24.576
36.864
49.152
73.728
(1)
(1) This system clock rate is not supported for the given sampling frequency.
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2 V
0.8 V
H
L
PARAMETERS
MIN
MAX
UNITS
t(SCY)
System clock pulse cycle time
13
ns
t(SCKH) System clock pulse duration, HIGH
0.4t(SCY)
ns
t(SCKL) System clock pulse duration, LOW
0.4t(SCY)
ns
Figure 24. System Clock Input Timing
Power-On and External Reset Functions
The DSD1792A includes a power-on reset function. Figure 25 shows the operation of this function. With VDD > 2 V, the
power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
VDD > 2 V. After the initialization period, the DSD1792A is set to its default reset state, as described in the MODE CONTROL
REGISTERS section of this data sheet.
The DSD1792A also includes an external reset capability using the RST input (pin 14). This allows an external controller
or master reset circuit to force the DSD1792A to initialize to its default reset state.
Figure 26 shows the external reset operation and timing. The RSTpin is set to logic 0 for a minimum of 20 ns. The RST
pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods.
Operation of the external reset is the same as that of the power-on reset. The external reset is especially useful in
applications where there is a delay between the DSD1792A power up and system clock activation.
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