參數(shù)資料
型號(hào)： DSM2180F3V90K6
廠商： 意法半導(dǎo)體
元件分類： 數(shù)字信號(hào)處理
英文描述： DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply)
中文描述： 帝斯曼（數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存）模擬器件公司的ADSP - 218X系列（5V電源）
文件頁(yè)數(shù)： 32/63頁(yè)
文件大?。?/td> 809K
代理商： DSM2180F3V90K6
DSM2180F3
32/63
DSP Bus Interface
The “no-glue logic” DSP Bus Interface allows di-
rect connection. DSP address, data, and control
signals connect directly to the DSM device. See
Figure 6 for typical connections.
DSP address, data and control signals are routed
to Flash memory, I/O control (
csiop
), OMCs, and
IMCs within the DMS. The DSP address range for
each of these components is specified in PSDsoft
Express
TM
.
I/O Ports
There are three programmable I/O ports: Ports B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press
TM
or by the DSP writing to on-chip registers
in the
csiop
block.
The topics discussed in this section are:
I
General Port architecture
I
Port operating modes
I
Port Configuration Registers (PCR)
I
Port Data Registers
I
Individual Port functionality.
General Port Architecture.
The general archi-
tecture of the I/O Port block is shown in Figure 19.
Individual Port architectures are shown in Figure
20 to Figure 23. In general, once the purpose for a
port pin has been defined in PSDsoft Express
TM
,
that pin is no longer available for other purposes.
Exceptions are noted.
Figure 19. General I/O Port Architecture
As shown in Figure 19, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits determined by PSDsoft Express.
Inputs to the multiplexer include the following:
I
Output data from the Data Out register (for MCU
I/O mode)
I
CPLD Macrocell output (OMC)
I
External Chip Selects ESC0-2 from the DPLD to
Port D pins only.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read by the
DSP. The Port Data Buffer (PDB) is connected to
the Internal Data Bus for feedback and can be
read by the DSP. The Data Out and Macrocell out-
I
DATA OUT
REG.
D
Q
D
Q
WR
WR
Macrocell Outputs
ENABLE PRODUCT TERM (.OE)
EXT CS
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
Input
Macrocell
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
AI04905B
相關(guān)PDF資料
PDF描述
DSM2180F3V90T6 DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSM2180F3V-90K6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
DSM2180F3V90T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply)
DSM2180F3V-90T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply)
DSM2190F4 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)
DSM2190F4V 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)
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