參數(shù)資料
型號(hào)： DSM2180F3V90K6
廠商： 意法半導(dǎo)體
元件分類： 數(shù)字信號(hào)處理
英文描述： DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply)
中文描述： 帝斯曼（數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存）模擬器件公司的ADSP - 218X系列（5V電源）
文件頁(yè)數(shù)： 41/63頁(yè)
文件大小： 809K
代理商： DSM2180F3V90K6
41/63
DSM2180F3
Figure 24. Reset (RESET) Timing
Power On Reset, Warm Reset, Power-down
Power On Reset.
Upon Power-up, the device re-
quires a Reset (
RESET
) pulse of duration t
NLNH-PO
after V
CC
is steady. During this time period, the de-
vice loads internal configurations, clears some of
the registers and sets the Flash memory into Op-
erating mode. After the rising edge of Reset (
RE-
SET
), the device remains in the Reset mode for an
additional period, t
OPR
, before the first memory ac-
cess is allowed.
The Flash memory is reset to the Read Array
mode upon Power-up. Sector Select FS0-FS7
must all be Low, Write Strobe (
WR
, CNTL0) High,
during Power On Reset for maximum security of
the data contents and to remove the possibility of
a byte being written on the first edge of Write
Strobe (
WR
, CNTL0). Any Flash memory Write cy-
cle initiation is prevented automatically when V
CC
is below V
LKO
.
Table 19. Status During Power-On Reset, Warm Reset and Power-down Mode
Warm Reset.
Once the device is up and running,
the device can be reset with a pulse of a much
shorter duration, t
NLNH
. The same t
OPR
period is
needed before the device is operational after
warm reset. Figure 24 shows the timing of the
Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset.
Ta-
ble 19 shows the I/O pin, register and PLD status
during Power On Reset, warm reset and Power-
down mode. PLD outputs are always valid during
warm reset, and they are valid in Power On Reset
once the internal device Configuration bits are
loaded. This loading of the device is completed
typically long before the V
CC
ramps up to operat-
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDsoft Express
equations.
Programming In-Circuit using JTAG ISP
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows programming of the entire DSM de-
vice or subsections (i.e. only Flash memory but not
the PLDs) without and participation of the DSP. A
blank DSM device soldered to a circuit board can
be completely programmed in 10 to 20 seconds.
The basic JTAG signals; TMS, TCK, TDI, and
TDO form the IEEE-1149.1 interface. The DSM
device does not implement the IEEE-1149.1
Boundary Scan functions. The DSM uses the
JTAG interface for ISP only. However, the DSM
device can reside in a standard JTAG chain with
other JTAG devices as it will remain in BYPASS
mode while other devices perform Boundary
Scan.
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to 0
Unchanged
Unchanged
OMC Flip-flop status
Cleared to 0 by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
All other registers
Cleared to 0
Cleared to 0
Unchanged
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參數(shù)描述
DSM2180F3V-90K6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
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