- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376997 > DSM2180F3V90K6 (意法半導體) DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) PDF資料下載
參數(shù)資料
| 型號： | DSM2180F3V90K6 |
| 廠商： | 意法半導體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號處理器系統(tǒng)內(nèi)存）模擬器件公司的ADSP - 218X系列（5V電源） |
| 文件頁數(shù)： | 34/63頁 |
| 文件大?。?/td> | 809K |
| 代理商： | DSM2180F3V90K6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁
DSM2180F3
34/63
port. The three Port Configuration Registers
(PCR), are shown in Table 12. Default is logic 0.
Table 12. Port Configuration Registers (PCR)
Note: 1. See Table 16 for Drive Register bit definition.
Data In Register.
The DSP may read the Data In
registers in the csiopblock at any time to deter-
mine the logic state of a Port pin. This will be the
state at the pin regardless of whether it is driven by
a source external to the DSM or driven internally
from the DSM device. Reading a logic zero for a bit
in a Data In register means the corresponding Port
pin is also at logic zero. Reading logic one means
the pin is logic one. Each bit in a Data In register
corresponds to an individual Port pin. For a given
Port, bit 0 in a Data In register corresponds to pin
0 of the Port. Example, bit 0 of the Data In register
for Port B corresponds to Port B pin PB0.
Data Out Register.
The DSP may write (or read)
the Data Out register in the csiop block at any
time. Writing the Data Out register will change the
logic state of a Port pin only if it is not driven or
controlled by the CPLD. Writing a logic zero to a bit
in a Data Out register will force the corresponding
Port pin to be logic zero. Writing logic one will drive
the pin to logic one. Each bit in the Data Out reg-
isters correspond to Port pins the same way as the
Data In registers described above. When some
pins of a Port are driven by the CPLD, writing to
the corresponding bit in a Data Out register will
have no effect as the CPLD overrides the Data Out
register.
Direction Register.
The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to 1 in the Direction Register
causes the corresponding pin to be an output, and
any bit set to 0 causes it to be an input. The default
mode for all port pins is input.
Table 13. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 14. Port Pin Direction Control, Output
Enable P.T. Defined
Table 15. Port Direction Assignment Example
Figure 20 and Figure 21 show the Port Architec-
ture diagrams for Ports B and C, respectively. The
direction of data flow for Ports B, and C are con-
trolled not only by the direction register, but also by
the output enable product term from the PLD AND
Array. If the output enable product term is not ac-
tive, the Direction Register has sole control of a
given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 15. Since
Port D only contains three pins (shown in Figure
23), the Direction Register for Port D has only the
three least significant bits active.
Drive Select Register.
The Drive Select Register
configures the pin driver as Open Drain or CMOS
(standard push/pull) for some port pins, and con-
trols the slew rate for the other port pins. An exter-
nal pull-up resistor should be used for pins
configured as Open Drain. Open Drain outputs are
diode clamped, thus the maximum voltage on an
pin configured as Open Drain is Vcc + 0.7V.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to 1. The default rate is standard slew.
Table 16 shows the Drive Register for Ports B, C,
and D. It summarizes which pins can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Register Name
Port
DSP Access
Data In
B,C,D
Read
Data Out
B,C,D
Write/Read
Direction
B,C,D
Write/Read
Drive Select
1
B,C,D
Write/Read
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
1
1
1
相關PDF資料 |
PDF描述 |
|---|---|
| DSM2180F3V90T6 | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| DSM2190F4 | 16-bit fixed point DSP with Flash |
| DSM2190F4V | 16-bit fixed point DSP with Flash |
| DSM2190F4V-15K6 | 16-bit fixed point DSP with Flash |
| DSM2190F4V-15T6 | 16-bit fixed point DSP with Flash |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSM2180F3V-90K6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| DSM2180F3V90T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply) |
| DSM2180F3V-90T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply) |
| DSM2190F4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply) |
| DSM2190F4V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply) |
發(fā)布緊急采購，3分鐘左右您將得到回復。