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參數(shù)資料
| 型號： | DSM2180F3V90K6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號處理器系統(tǒng)內(nèi)存）模擬器件公司的ADSP - 218X系列（5V電源） |
| 文件頁數(shù)： | 9/63頁 |
| 文件大?。?/td> | 809K |
| 代理商： | DSM2180F3V90K6 |
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DSM2180F3
without clocking or latching. The DSP may read
the IMCs at any time.
Runtime Control Registers
A block of 256 bytes is decoded inside the DSM
device as DSM control and status registers. 27
registers are used in the block of 256 locations to
control the output state of I/O pins, to read I/O
pins, to control power management, to read/write
macrocells, and other functions at runtime. See
Table 4 for description. The base address of these
256 locations is referred to in this data sheet as
csiop (Chip Select I/O Port). Individual registers
within this block are accessed with an offset from
the base address. The DSP accesses csiopregis-
ters using I/O memory with the
IOMS
strobe. csiop
registers are accessed as bytes, so only the lower
half of a DSP I/O word is used during access.
Memory Page Register
This 8-bit register can be loaded and read by the
DSP at runtime as one of the csiopregisters. Its
outputs feed directly into the PLDs. The page reg-
ister is a powerful feature that allows the DSP to
access all 128K Bytes of DSM Flash memory in
16K byte pages. This size matches the 16K loca-
tion data overlay window the ADSP-218X family.
Page register outputs may also be used as CPLD
inputs for general use.
I/O Ports
The DSM has 19 individually configurable I/O pins
distributed over the three ports (Ports B, C, and D).
Each I/O pin can be individually configured for dif-
ferent functions such as standard MCU I/O ports
or PLD I/O on a pin by pin basis. (MCU I/O means
that for each pin, its output state can be controlled
or its input value can be read by the DSP at runt-
ime using the csiop registers like an MCU would
do.)
Port C hosts the JTAG ISP signals. Since JTAG-
ISP does not occur frequently during the life of a
product, those Port C pins are under-utilized. In
applications that need every I/O pin, JTAG signals
can be multiplexed with general I/O signals to use
them for I/O when not performing ISP. See section
titled “Programming In-Circuit using JTAG ISP” on
page 41 for muxing JTAG pins on Port C, and Ap-
plication Note
AN1153
.
The static configuration of all Port pins is defined
with the PSDsoft Express
TM
software develop-
ment tool. The dynamic action of the Ports pins is
controlled by DSP runtime software.
JTAG ISP Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows programming of the entire DSM
device or subsections (that is, only Flash memory
but not the PLDs) without the participation of the
DSP. A blank DSM device soldered to a circuit
board can be completely programmed in 10 to 20
seconds. The basic JTAG signals; TMS, TCK,
TDI, and TDO form the IEEE-1149.1 interface.
The DSM device does not implement the IEEE-
1149.1 Boundary Scan functions. The DSM uses
the JTAG interface for ISP only. However, the
DSM device can reside in a standard JTAG chain
with other JTAG devices and it will remain in BY-
PASS mode while other devices perform Bound-
ary Scan.
ISP programming time can be reduced as much as
30% by using two more signals on Port C, TSTAT
and TERR in addition to TMS, TCK, TDI and TDO.
The FlashLINK
TM
JTAG
programming cable is
available from STMicroelectronics for $59USD
and PSDsoft Express software is available at no
charge from www.psdst.com. That is all that is
needed to program a DSM device using the paral-
lel port on any PC or note-book. See section titled
“Programming In-Circuit using JTAG ISP” on page
41.
Power Management
The DSM has bits in
csiop
control registers that
are configured at run-time by the DSP to reduce
power consumption of the CPLD. The Turbo bit in
the PMMR0 register can be set to logic 1 and the
CPLD will go to Non-Turbo mode, meaning it will
latch its outputs and go to sleep until the next tran-
sition on its inputs. There is a slight penalty in PLD
performance (longer propagation delay), but sig-
nificant power savings are realized.
Additionally, bits in two
csiop
registers can be set
by the DSP to selectively block signals from enter-
ing the CPLD which reduces power consumption.
See section titled “Power Management” on page
39.
Security and NVM Sector Protection
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copy-
ing. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memory and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again.
Additionally, the contents of each individual Flash
memory sector can be write protected (sector pro-
tection) by configuration with PSDsoft Express
TM
.
This is typically used to protect DSP boot code
from being corrupted by inadvertent writes to
Flash memory from the DSP.
Pin Assignments
Pin assignment are shown for the 52-pin PLCC
package in Figure 2, and the 52-pin PQFP pack-
age in Figure 3.
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參數(shù)描述 |
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| DSM2180F3V-90K6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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